public:
virtual ~Delegate() = default;
- virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
+ virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
};
private:
/// Live in values are typically arguments in registers. LiveIn values are
/// allowed to have virtual registers associated with them, stored in the
/// second element.
- std::vector<std::pair<unsigned, unsigned>> LiveIns;
+ std::vector<std::pair<MCRegister, Register>> LiveIns;
public:
explicit MachineRegisterInfo(MachineFunction *MF);
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
/// Verify the sanity of the use list for Reg.
- void verifyUseList(unsigned Reg) const;
+ void verifyUseList(Register Reg) const;
/// Verify the use list of all registers.
void verifyUseLists() const;
/// register.
using reg_iterator =
defusechain_iterator<true, true, false, true, false, false>;
- reg_iterator reg_begin(unsigned RegNo) const {
+ reg_iterator reg_begin(Register RegNo) const {
return reg_iterator(getRegUseDefListHead(RegNo));
}
static reg_iterator reg_end() { return reg_iterator(nullptr); }
- inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
+ inline iterator_range<reg_iterator> reg_operands(Register Reg) const {
return make_range(reg_begin(Reg), reg_end());
}
/// of the specified register, stepping by MachineInstr.
using reg_instr_iterator =
defusechain_instr_iterator<true, true, false, false, true, false>;
- reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
+ reg_instr_iterator reg_instr_begin(Register RegNo) const {
return reg_instr_iterator(getRegUseDefListHead(RegNo));
}
static reg_instr_iterator reg_instr_end() {
}
inline iterator_range<reg_instr_iterator>
- reg_instructions(unsigned Reg) const {
+ reg_instructions(Register Reg) const {
return make_range(reg_instr_begin(Reg), reg_instr_end());
}
/// of the specified register, stepping by bundle.
using reg_bundle_iterator =
defusechain_instr_iterator<true, true, false, false, false, true>;
- reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
+ reg_bundle_iterator reg_bundle_begin(Register RegNo) const {
return reg_bundle_iterator(getRegUseDefListHead(RegNo));
}
static reg_bundle_iterator reg_bundle_end() {
return reg_bundle_iterator(nullptr);
}
- inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
+ inline iterator_range<reg_bundle_iterator> reg_bundles(Register Reg) const {
return make_range(reg_bundle_begin(Reg), reg_bundle_end());
}
/// reg_empty - Return true if there are no instructions using or defining the
/// specified register (it may be live-in).
- bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
+ bool reg_empty(Register RegNo) const { return reg_begin(RegNo) == reg_end(); }
/// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
/// of the specified register, skipping those marked as Debug.
}
inline iterator_range<reg_nodbg_iterator>
- reg_nodbg_operands(unsigned Reg) const {
+ reg_nodbg_operands(Register Reg) const {
return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
}
/// skipping those marked as Debug.
using reg_instr_nodbg_iterator =
defusechain_instr_iterator<true, true, true, false, true, false>;
- reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
+ reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const {
return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
}
static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
}
inline iterator_range<reg_instr_nodbg_iterator>
- reg_nodbg_instructions(unsigned Reg) const {
+ reg_nodbg_instructions(Register Reg) const {
return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end());
}
/// skipping those marked as Debug.
using reg_bundle_nodbg_iterator =
defusechain_instr_iterator<true, true, true, false, false, true>;
- reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
+ reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const {
return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
}
static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
}
inline iterator_range<reg_bundle_nodbg_iterator>
- reg_nodbg_bundles(unsigned Reg) const {
+ reg_nodbg_bundles(Register Reg) const {
return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end());
}
/// def_iterator/def_begin/def_end - Walk all defs of the specified register.
using def_iterator =
defusechain_iterator<false, true, false, true, false, false>;
- def_iterator def_begin(unsigned RegNo) const {
+ def_iterator def_begin(Register RegNo) const {
return def_iterator(getRegUseDefListHead(RegNo));
}
static def_iterator def_end() { return def_iterator(nullptr); }
- inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
+ inline iterator_range<def_iterator> def_operands(Register Reg) const {
return make_range(def_begin(Reg), def_end());
}
/// specified register, stepping by MachineInst.
using def_instr_iterator =
defusechain_instr_iterator<false, true, false, false, true, false>;
- def_instr_iterator def_instr_begin(unsigned RegNo) const {
+ def_instr_iterator def_instr_begin(Register RegNo) const {
return def_instr_iterator(getRegUseDefListHead(RegNo));
}
static def_instr_iterator def_instr_end() {
}
inline iterator_range<def_instr_iterator>
- def_instructions(unsigned Reg) const {
+ def_instructions(Register Reg) const {
return make_range(def_instr_begin(Reg), def_instr_end());
}
/// specified register, stepping by bundle.
using def_bundle_iterator =
defusechain_instr_iterator<false, true, false, false, false, true>;
- def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
+ def_bundle_iterator def_bundle_begin(Register RegNo) const {
return def_bundle_iterator(getRegUseDefListHead(RegNo));
}
static def_bundle_iterator def_bundle_end() {
return def_bundle_iterator(nullptr);
}
- inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
+ inline iterator_range<def_bundle_iterator> def_bundles(Register Reg) const {
return make_range(def_bundle_begin(Reg), def_bundle_end());
}
/// def_empty - Return true if there are no instructions defining the
/// specified register (it may be live-in).
- bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
+ bool def_empty(Register RegNo) const { return def_begin(RegNo) == def_end(); }
- StringRef getVRegName(unsigned Reg) const {
+ StringRef getVRegName(Register Reg) const {
return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : "";
}
- void insertVRegByName(StringRef Name, unsigned Reg) {
+ void insertVRegByName(StringRef Name, Register Reg) {
assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) &&
"Named VRegs Must be Unique.");
if (!Name.empty()) {
/// Return true if there is exactly one operand defining the specified
/// register.
- bool hasOneDef(unsigned RegNo) const {
+ bool hasOneDef(Register RegNo) const {
def_iterator DI = def_begin(RegNo);
if (DI == def_end())
return false;
/// use_iterator/use_begin/use_end - Walk all uses of the specified register.
using use_iterator =
defusechain_iterator<true, false, false, true, false, false>;
- use_iterator use_begin(unsigned RegNo) const {
+ use_iterator use_begin(Register RegNo) const {
return use_iterator(getRegUseDefListHead(RegNo));
}
static use_iterator use_end() { return use_iterator(nullptr); }
- inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
+ inline iterator_range<use_iterator> use_operands(Register Reg) const {
return make_range(use_begin(Reg), use_end());
}
/// specified register, stepping by MachineInstr.
using use_instr_iterator =
defusechain_instr_iterator<true, false, false, false, true, false>;
- use_instr_iterator use_instr_begin(unsigned RegNo) const {
+ use_instr_iterator use_instr_begin(Register RegNo) const {
return use_instr_iterator(getRegUseDefListHead(RegNo));
}
static use_instr_iterator use_instr_end() {
}
inline iterator_range<use_instr_iterator>
- use_instructions(unsigned Reg) const {
+ use_instructions(Register Reg) const {
return make_range(use_instr_begin(Reg), use_instr_end());
}
/// specified register, stepping by bundle.
using use_bundle_iterator =
defusechain_instr_iterator<true, false, false, false, false, true>;
- use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
+ use_bundle_iterator use_bundle_begin(Register RegNo) const {
return use_bundle_iterator(getRegUseDefListHead(RegNo));
}
static use_bundle_iterator use_bundle_end() {
return use_bundle_iterator(nullptr);
}
- inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
+ inline iterator_range<use_bundle_iterator> use_bundles(Register Reg) const {
return make_range(use_bundle_begin(Reg), use_bundle_end());
}
/// use_empty - Return true if there are no instructions using the specified
/// register.
- bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
+ bool use_empty(Register RegNo) const { return use_begin(RegNo) == use_end(); }
/// hasOneUse - Return true if there is exactly one instruction using the
/// specified register.
- bool hasOneUse(unsigned RegNo) const {
+ bool hasOneUse(Register RegNo) const {
use_iterator UI = use_begin(RegNo);
if (UI == use_end())
return false;
/// specified register, skipping those marked as Debug.
using use_nodbg_iterator =
defusechain_iterator<true, false, true, true, false, false>;
- use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
+ use_nodbg_iterator use_nodbg_begin(Register RegNo) const {
return use_nodbg_iterator(getRegUseDefListHead(RegNo));
}
static use_nodbg_iterator use_nodbg_end() {
}
inline iterator_range<use_nodbg_iterator>
- use_nodbg_operands(unsigned Reg) const {
+ use_nodbg_operands(Register Reg) const {
return make_range(use_nodbg_begin(Reg), use_nodbg_end());
}
/// those marked as Debug.
using use_instr_nodbg_iterator =
defusechain_instr_iterator<true, false, true, false, true, false>;
- use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
+ use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const {
return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
}
static use_instr_nodbg_iterator use_instr_nodbg_end() {
}
inline iterator_range<use_instr_nodbg_iterator>
- use_nodbg_instructions(unsigned Reg) const {
+ use_nodbg_instructions(Register Reg) const {
return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end());
}
/// those marked as Debug.
using use_bundle_nodbg_iterator =
defusechain_instr_iterator<true, false, true, false, false, true>;
- use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
+ use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const {
return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
}
static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
}
inline iterator_range<use_bundle_nodbg_iterator>
- use_nodbg_bundles(unsigned Reg) const {
+ use_nodbg_bundles(Register Reg) const {
return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end());
}
/// use_nodbg_empty - Return true if there are no non-Debug instructions
/// using the specified register.
- bool use_nodbg_empty(unsigned RegNo) const {
+ bool use_nodbg_empty(Register RegNo) const {
return use_nodbg_begin(RegNo) == use_nodbg_end();
}
/// hasOneNonDBGUse - Return true if there is exactly one non-Debug
/// use of the specified register.
- bool hasOneNonDBGUse(unsigned RegNo) const;
+ bool hasOneNonDBGUse(Register RegNo) const;
/// hasOneNonDBGUse - Return true if there is exactly one non-Debug
/// instruction using the specified register. Said instruction may have
/// multiple uses.
- bool hasOneNonDBGUser(unsigned RegNo) const;
-
+ bool hasOneNonDBGUser(Register RegNo) const;
+
/// replaceRegWith - Replace all instances of FromReg with ToReg in the
/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
/// except that it also changes any definitions of the register as well.
/// Note that if ToReg is a physical register the function will replace and
/// apply sub registers to ToReg in order to obtain a final/proper physical
/// register.
- void replaceRegWith(unsigned FromReg, unsigned ToReg);
+ void replaceRegWith(Register FromReg, Register ToReg);
/// getVRegDef - Return the machine instr that defines the specified virtual
/// register or null if none is found. This assumes that the code is in SSA
/// form, so there should only be one definition.
- MachineInstr *getVRegDef(unsigned Reg) const;
+ MachineInstr *getVRegDef(Register Reg) const;
/// getUniqueVRegDef - Return the unique machine instr that defines the
/// specified virtual register or null if none is found. If there are
/// multiple definitions or no definition, return null.
- MachineInstr *getUniqueVRegDef(unsigned Reg) const;
+ MachineInstr *getUniqueVRegDef(Register Reg) const;
/// clearKillFlags - Iterate over all the uses of the given register and
/// clear the kill flag from the MachineOperand. This function is used by
/// optimization passes which extend register lifetimes and need only
/// preserve conservative kill flag information.
- void clearKillFlags(unsigned Reg) const;
+ void clearKillFlags(Register Reg) const;
- void dumpUses(unsigned RegNo) const;
+ void dumpUses(Register RegNo) const;
/// Returns true if PhysReg is unallocatable and constant throughout the
/// function. Writing to a constant register has no effect.
- bool isConstantPhysReg(unsigned PhysReg) const;
+ bool isConstantPhysReg(MCRegister PhysReg) const;
/// Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg
/// returns true. This is a utility member function.
- bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const;
+ bool isCallerPreservedOrConstPhysReg(MCRegister PhysReg) const;
/// Get an iterator over the pressure sets affected by the given physical or
/// virtual register. If RegUnit is physical, it must be a register unit (from
/// None of this condition is possible without GlobalISel for now.
/// In other words, if GlobalISel is not used or if the query happens after
/// the select pass, using getRegClass is safe.
- const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const {
+ const TargetRegisterClass *getRegClassOrNull(Register Reg) const {
const RegClassOrRegBank &Val = VRegInfo[Reg].first;
return Val.dyn_cast<const TargetRegisterClass *>();
}
/// a register bank or has been assigned a register class.
/// \note It is possible to get the register bank from the register class via
/// RegisterBankInfo::getRegBankFromRegClass.
- const RegisterBank *getRegBankOrNull(unsigned Reg) const {
+ const RegisterBank *getRegBankOrNull(Register Reg) const {
const RegClassOrRegBank &Val = VRegInfo[Reg].first;
return Val.dyn_cast<const RegisterBank *>();
}
/// Return the register bank or register class of \p Reg.
/// \note Before the register bank gets assigned (i.e., before the
/// RegBankSelect pass) \p Reg may not have either.
- const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const {
+ const RegClassOrRegBank &getRegClassOrRegBank(Register Reg) const {
return VRegInfo[Reg].first;
}
/// setRegClass - Set the register class of the specified virtual register.
- void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
+ void setRegClass(Register Reg, const TargetRegisterClass *RC);
/// Set the register bank to \p RegBank for \p Reg.
- void setRegBank(unsigned Reg, const RegisterBank &RegBank);
+ void setRegBank(Register Reg, const RegisterBank &RegBank);
- void setRegClassOrRegBank(unsigned Reg,
+ void setRegClassOrRegBank(Register Reg,
const RegClassOrRegBank &RCOrRB){
VRegInfo[Reg].first = RCOrRB;
}
/// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
/// InstructionSelect pass and constrainRegAttrs in every other pass,
/// including non-select passes of GlobalISel, instead.
- const TargetRegisterClass *constrainRegClass(unsigned Reg,
+ const TargetRegisterClass *constrainRegClass(Register Reg,
const TargetRegisterClass *RC,
unsigned MinNumRegs = 0);
/// \note Use this method instead of constrainRegClass and
/// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
/// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
- bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg,
+ bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
unsigned MinNumRegs = 0);
/// recomputeRegClass - Try to find a legal super-class of Reg's register
/// This method can be used after constraints have been removed from a
/// virtual register, for example after removing instructions or splitting
/// the live range.
- bool recomputeRegClass(unsigned Reg);
+ bool recomputeRegClass(Register Reg);
/// createVirtualRegister - Create and return a new virtual register in the
/// function with the specified register class.
/// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
/// (target independent) virtual register.
- LLT getType(unsigned Reg) const {
+ LLT getType(Register Reg) const {
if (Register::isVirtualRegister(Reg) && VRegToType.inBounds(Reg))
return VRegToType[Reg];
return LLT{};
}
/// Set the low-level type of \p VReg to \p Ty.
- void setType(unsigned VReg, LLT Ty);
+ void setType(Register VReg, LLT Ty);
/// Create and return a new generic virtual register with low-level
/// type \p Ty.
/// setRegAllocationHint - Specify a register allocation hint for the
/// specified virtual register. This is typically used by target, and in case
/// of an earlier hint it will be overwritten.
- void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
+ void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) {
assert(Register::isVirtualRegister(VReg));
RegAllocHints[VReg].first = Type;
RegAllocHints[VReg].second.clear();
/// addRegAllocationHint - Add a register allocation hint to the hints
/// vector for VReg.
- void addRegAllocationHint(unsigned VReg, unsigned PrefReg) {
+ void addRegAllocationHint(Register VReg, Register PrefReg) {
assert(Register::isVirtualRegister(VReg));
RegAllocHints[VReg].second.push_back(PrefReg);
}
/// Specify the preferred (target independent) register allocation hint for
/// the specified virtual register.
- void setSimpleHint(unsigned VReg, unsigned PrefReg) {
+ void setSimpleHint(Register VReg, Register PrefReg) {
setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
}
/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
/// specified register as undefined which causes the DBG_VALUE to be
/// deleted during LiveDebugVariables analysis.
- void markUsesInDebugValueAsUndef(unsigned Reg) const;
+ void markUsesInDebugValueAsUndef(Register Reg) const;
/// updateDbgUsersToReg - Update a collection of DBG_VALUE instructions
/// to refer to the designated register.
- void updateDbgUsersToReg(unsigned Reg,
+ void updateDbgUsersToReg(Register Reg,
ArrayRef<MachineInstr*> Users) const {
for (MachineInstr *MI : Users) {
assert(MI->isDebugInstr());
/// ignored, to consider them pass 'true' for optional parameter
/// SkipNoReturnDef. The register is also considered modified when it is set
/// in the UsedPhysRegMask.
- bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef = false) const;
+ bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false) const;
/// Return true if the specified register is modified or read in this
/// function. This checks that no machine operands exist for the register or
/// any of its aliases. The register is also considered used when it is set
/// in the UsedPhysRegMask.
- bool isPhysRegUsed(unsigned PhysReg) const;
+ bool isPhysRegUsed(MCRegister PhysReg) const;
/// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
/// This corresponds to the bit mask attached to register mask operands.
/// addLiveIn - Add the specified register as a live-in. Note that it
/// is an error to add the same register to the same set more than once.
- void addLiveIn(unsigned Reg, unsigned vreg = 0) {
+ void addLiveIn(MCRegister Reg, Register vreg = Register()) {
LiveIns.push_back(std::make_pair(Reg, vreg));
}
// Iteration support for the live-ins set. It's kept in sorted order
// by register number.
using livein_iterator =
- std::vector<std::pair<unsigned,unsigned>>::const_iterator;
+ std::vector<std::pair<MCRegister,Register>>::const_iterator;
livein_iterator livein_begin() const { return LiveIns.begin(); }
livein_iterator livein_end() const { return LiveIns.end(); }
bool livein_empty() const { return LiveIns.empty(); }
- ArrayRef<std::pair<unsigned, unsigned>> liveins() const {
+ ArrayRef<std::pair<MCRegister, Register>> liveins() const {
return LiveIns;
}
- bool isLiveIn(unsigned Reg) const;
+ bool isLiveIn(Register Reg) const;
/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
/// corresponding live-in physical register.
- unsigned getLiveInPhysReg(unsigned VReg) const;
+ unsigned getLiveInPhysReg(Register VReg) const;
/// getLiveInVirtReg - If PReg is a live-in physical register, return the
/// corresponding live-in physical register.
- unsigned getLiveInVirtReg(unsigned PReg) const;
+ unsigned getLiveInVirtReg(MCRegister PReg) const;
/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
/// into the given entry block.
/// Returns a mask covering all bits that can appear in lane masks of
/// subregisters of the virtual register @p Reg.
- LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const;
+ LaneBitmask getMaxLaneMaskForVReg(Register Reg) const;
/// defusechain_iterator - This class provides iterator support for machine
/// operands in the function that use or define a specific register. If
/// setRegClass - Set the register class of the specified virtual register.
///
void
-MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
+MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) {
assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
VRegInfo[Reg].first = RC;
}
-void MachineRegisterInfo::setRegBank(unsigned Reg,
+void MachineRegisterInfo::setRegBank(Register Reg,
const RegisterBank &RegBank) {
VRegInfo[Reg].first = &RegBank;
}
static const TargetRegisterClass *
-constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg,
+constrainRegClass(MachineRegisterInfo &MRI, Register Reg,
const TargetRegisterClass *OldRC,
const TargetRegisterClass *RC, unsigned MinNumRegs) {
if (OldRC == RC)
}
const TargetRegisterClass *
-MachineRegisterInfo::constrainRegClass(unsigned Reg,
+MachineRegisterInfo::constrainRegClass(Register Reg,
const TargetRegisterClass *RC,
unsigned MinNumRegs) {
return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
}
bool
-MachineRegisterInfo::constrainRegAttrs(unsigned Reg,
- unsigned ConstrainingReg,
+MachineRegisterInfo::constrainRegAttrs(Register Reg,
+ Register ConstrainingReg,
unsigned MinNumRegs) {
const LLT RegTy = getType(Reg);
const LLT ConstrainingRegTy = getType(ConstrainingReg);
}
bool
-MachineRegisterInfo::recomputeRegClass(unsigned Reg) {
+MachineRegisterInfo::recomputeRegClass(Register Reg) {
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
const TargetRegisterClass *OldRC = getRegClass(Reg);
const TargetRegisterClass *NewRC =
}
unsigned MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) {
- unsigned Reg = Register::index2VirtReg(getNumVirtRegs());
+ Register Reg = Register::index2VirtReg(getNumVirtRegs());
VRegInfo.grow(Reg);
RegAllocHints.grow(Reg);
insertVRegByName(Name, Reg);
"Virtual register RegClass must be allocatable.");
// New virtual register number.
- unsigned Reg = createIncompleteVirtualRegister(Name);
+ Register Reg = createIncompleteVirtualRegister(Name);
VRegInfo[Reg].first = RegClass;
if (TheDelegate)
TheDelegate->MRI_NoteNewVirtualRegister(Reg);
Register MachineRegisterInfo::cloneVirtualRegister(Register VReg,
StringRef Name) {
- unsigned Reg = createIncompleteVirtualRegister(Name);
+ Register Reg = createIncompleteVirtualRegister(Name);
VRegInfo[Reg].first = VRegInfo[VReg].first;
setType(Reg, getType(VReg));
if (TheDelegate)
return Reg;
}
-void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) {
+void MachineRegisterInfo::setType(Register VReg, LLT Ty) {
VRegToType.grow(VReg);
VRegToType[VReg] = Ty;
}
Register
MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) {
// New virtual register number.
- unsigned Reg = createIncompleteVirtualRegister(Name);
+ Register Reg = createIncompleteVirtualRegister(Name);
// FIXME: Should we use a dummy register class?
VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
setType(Reg, Ty);
void MachineRegisterInfo::clearVirtRegs() {
#ifndef NDEBUG
for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
- unsigned Reg = Register::index2VirtReg(i);
+ Register Reg = Register::index2VirtReg(i);
if (!VRegInfo[Reg].second)
continue;
verifyUseList(Reg);
I.second = 0;
}
-void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
+void MachineRegisterInfo::verifyUseList(Register Reg) const {
#ifndef NDEBUG
bool Valid = true;
for (MachineOperand &M : reg_operands(Reg)) {
/// except that it also changes any definitions of the register as well.
/// If ToReg is a physical register we apply the sub register to obtain the
/// final/proper physical register.
-void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
+void MachineRegisterInfo::replaceRegWith(Register FromReg, Register ToReg) {
assert(FromReg != ToReg && "Cannot replace a reg with itself");
const TargetRegisterInfo *TRI = getTargetRegisterInfo();
/// getVRegDef - Return the machine instr that defines the specified virtual
/// register or null if none is found. This assumes that the code is in SSA
/// form, so there should only be one definition.
-MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
+MachineInstr *MachineRegisterInfo::getVRegDef(Register Reg) const {
// Since we are in SSA form, we can use the first definition.
def_instr_iterator I = def_instr_begin(Reg);
assert((I.atEnd() || std::next(I) == def_instr_end()) &&
/// getUniqueVRegDef - Return the unique machine instr that defines the
/// specified virtual register or null if none is found. If there are
/// multiple definitions or no definition, return null.
-MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
+MachineInstr *MachineRegisterInfo::getUniqueVRegDef(Register Reg) const {
if (def_empty(Reg)) return nullptr;
def_instr_iterator I = def_instr_begin(Reg);
if (std::next(I) != def_instr_end())
return &*I;
}
-bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
+bool MachineRegisterInfo::hasOneNonDBGUse(Register RegNo) const {
use_nodbg_iterator UI = use_nodbg_begin(RegNo);
if (UI == use_nodbg_end())
return false;
return ++UI == use_nodbg_end();
}
-bool MachineRegisterInfo::hasOneNonDBGUser(unsigned RegNo) const {
+bool MachineRegisterInfo::hasOneNonDBGUser(Register RegNo) const {
use_instr_nodbg_iterator UI = use_instr_nodbg_begin(RegNo);
if (UI == use_instr_nodbg_end())
return false;
/// clear the kill flag from the MachineOperand. This function is used by
/// optimization passes which extend register lifetimes and need only
/// preserve conservative kill flag information.
-void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
+void MachineRegisterInfo::clearKillFlags(Register Reg) const {
for (MachineOperand &MO : use_operands(Reg))
MO.setIsKill(false);
}
-bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
+bool MachineRegisterInfo::isLiveIn(Register Reg) const {
for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
- if (I->first == Reg || I->second == Reg)
+ if ((Register)I->first == Reg || I->second == Reg)
return true;
return false;
}
/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
/// corresponding live-in physical register.
-unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
+unsigned MachineRegisterInfo::getLiveInPhysReg(Register VReg) const {
for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
if (I->second == VReg)
return I->first;
/// getLiveInVirtReg - If PReg is a live-in physical register, return the
/// corresponding live-in physical register.
-unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
+unsigned MachineRegisterInfo::getLiveInVirtReg(MCRegister PReg) const {
for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
if (I->first == PReg)
return I->second;
}
}
-LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const {
+LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(Register Reg) const {
// Lane masks are only defined for vregs.
assert(Register::isVirtualRegister(Reg));
const TargetRegisterClass &TRC = *getRegClass(Reg);
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(unsigned Reg) const {
+LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const {
for (MachineInstr &I : use_instructions(Reg))
I.dump();
}
"Invalid ReservedRegs vector from target");
}
-bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
+bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
assert(Register::isPhysicalRegister(PhysReg));
const TargetRegisterInfo *TRI = getTargetRegisterInfo();
}
bool
-MachineRegisterInfo::isCallerPreservedOrConstPhysReg(unsigned PhysReg) const {
+MachineRegisterInfo::isCallerPreservedOrConstPhysReg(MCRegister PhysReg) const {
const TargetRegisterInfo *TRI = getTargetRegisterInfo();
return isConstantPhysReg(PhysReg) ||
TRI->isCallerPreservedPhysReg(PhysReg, *MF);
/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
/// specified register as undefined which causes the DBG_VALUE to be
/// deleted during LiveDebugVariables analysis.
-void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const {
+void MachineRegisterInfo::markUsesInDebugValueAsUndef(Register Reg) const {
// Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
MachineRegisterInfo::use_instr_iterator nextI;
for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end();
!Called->hasFnAttribute(Attribute::NoUnwind));
}
-bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg,
+bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg,
bool SkipNoReturnDef) const {
if (UsedPhysRegMask.test(PhysReg))
return true;
return false;
}
-bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const {
+bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg) const {
if (UsedPhysRegMask.test(PhysReg))
return true;
const TargetRegisterInfo *TRI = getTargetRegisterInfo();