Just mask higher bits off, which returns the same set of 3-bit register
encodings of { 0, 1, 2, 3, 4, 5, 6, 7 } for the allowed 5-bit encodings
of { 16, 17, 2, 3, 4, 5, 6, 7 }. Input has already been validated with
OP16_VALID_REG.
bfd/
* elfxx-mips.c (BZ16_REG_FIELD): Simplify calculation.
2016-01-24 Maciej W. Rozycki <macro@imgtec.com>
+ * elfxx-mips.c (BZ16_REG_FIELD): Simplify calculation.
+
+2016-01-24 Maciej W. Rozycki <macro@imgtec.com>
+
* elfxx-mips.c (BZ16_REG): Correct calculation.
2016-01-21 Nick Clifton <nickc@redhat.com>
/* Switch between a 5-bit register index and its 3-bit shorthand. */
#define BZ16_REG(opcode) ((((((opcode) >> 7) & 7) + 0x1e) & 0xf) + 2)
-#define BZ16_REG_FIELD(r) \
- (((2 <= (r) && (r) <= 7) ? (r) : ((r) - 16)) << 7)
+#define BZ16_REG_FIELD(r) (((r) & 7) << 7)
/* 32-bit instructions with a delay slot. */