RISC-V: Skip setting up PMPs on traps

The RISC-V ISA manual says that PMPs are WARL, but it appears the K210
doesn't implement them and instead traps on the unsupported accesses.
This patch handles those traps by just skipping the PMP
initialization entirely, under the theory that machines that trap on PMP
accesses must allow memory accesses as otherwise they're pretty useless.

Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 98a406474e7da5340ce605fdcdf1a7e57e02d184..7ed1b22950fdba3b0f82d68c2330e9da00958b6b 100644 (file)
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -161,11 +161,20 @@ ENTRY(_start_kernel)
        /* Reset all registers except ra, a0, a1 */
        call reset_regs
 
-       /* Setup a PMP to permit access to all of memory. */
+       /*
+        * Setup a PMP to permit access to all of memory.  Some machines may
+        * not implement PMPs, so we set up a quick trap handler to just skip
+        * touching the PMPs on any trap.
+        */
+       la a0, pmp_done
+       csrw CSR_TVEC, a0
+
        li a0, -1
        csrw CSR_PMPADDR0, a0
        li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X)
        csrw CSR_PMPCFG0, a0
+.align 2
+pmp_done:
 
        /*
         * The hartid in a0 is expected later on, and we have no firmware