sun6i: Add gmac support for sun6i boards

Hookup the gmac found on the sun6i / A31 SoCs.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 50a4b69..3599054 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -204,6 +204,7 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_USB_EHCI1      27
 #define AHB_GATE_OFFSET_USB_EHCI0      26
 #define AHB_GATE_OFFSET_MCTL           14
+#define AHB_GATE_OFFSET_GMAC           17
 #define AHB_GATE_OFFSET_MMC3           11
 #define AHB_GATE_OFFSET_MMC2           10
 #define AHB_GATE_OFFSET_MMC1           9
@@ -229,6 +230,12 @@ struct sunxi_ccm_reg {
 #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
 #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
 
+#define CCM_GMAC_CTRL_TX_CLK_SRC_MII   0x0
+#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
+#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
+#define CCM_GMAC_CTRL_GPIT_MII         (0x0 << 2)
+#define CCM_GMAC_CTRL_GPIT_RGMII       (0x1 << 2)
+
 #define MDFS_CLK_DEFAULT               0x81000002 /* PLL6 / 3 */
 
 #define CCM_DRAMCLK_CFG_DIV0(x)                ((x - 1) << 8)
@@ -264,6 +271,7 @@ struct sunxi_ccm_reg {
 #define MBUS_CLK_DEFAULT               0x81000001 /* PLL6 / 2 */
 
 /* ahb_reset0 offsets */
+#define AHB_RESET_OFFSET_GMAC          17
 #define AHB_RESET_OFFSET_MCTL          14
 #define AHB_RESET_OFFSET_MMC3          11
 #define AHB_RESET_OFFSET_MMC2          10

diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index bdee89e..2c92b5c 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -99,9 +99,13 @@
 
 #define SUNXI_SCR_BASE                 0x01c2c400
 
+#ifndef CONFIG_MACH_SUN6I
 #define SUNXI_GPS_BASE                 0x01c30000
 #define SUNXI_MALI400_BASE             0x01c40000
 #define SUNXI_GMAC_BASE                        0x01c50000
+#else
+#define SUNXI_GMAC_BASE                        0x01c30000
+#endif
 
 #define SUNXI_DRAM_COM_BASE            0x01c62000
 #define SUNXI_DRAM_CTL0_BASE           0x01c63000

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index c734cf0..366c0dc 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -134,6 +134,7 @@ enum sunxi_gpio_number {
 #define SUNXI_GPIO_OUTPUT      1
 
 #define SUNXI_GPA0_EMAC                2
+#define SUN6I_GPA0_GMAC                2
 #define SUN7I_GPA0_GMAC                5
 
 #define SUNXI_GPB0_TWI0                2

diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 051aca0..571bc9e 100644 (file)
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -13,7 +13,12 @@ int sunxi_gmac_initialize(bd_t *bis)
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
        /* Set up clock gating */
+#ifndef CONFIG_MACH_SUN6I
        setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
+#else
+       setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
+       setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
+#endif
 
        /* Set MII clock */
 #ifdef CONFIG_RGMII
@@ -33,6 +38,7 @@ int sunxi_gmac_initialize(bd_t *bis)
        setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);
 #endif
 
+#ifndef CONFIG_MACH_SUN6I
        /* Configure pin mux settings for GMAC */
        for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
 #ifdef CONFIG_RGMII
@@ -43,9 +49,48 @@ int sunxi_gmac_initialize(bd_t *bis)
                sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
                sunxi_gpio_set_drv(pin, 3);
        }
+#elif defined CONFIG_RGMII
+       /* Configure sun6i RGMII mode pin mux settings */
+       for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_drv(pin, 3);
+       }
+       for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_drv(pin, 3);
+       }
+       for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_drv(pin, 3);
+       }
+       for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_drv(pin, 3);
+       }
+#elif defined CONFIG_GMII
+       /* Configure sun6i GMII mode pin mux settings */
+       for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_drv(pin, 2);
+       }
+#else
+       /* Configure sun6i MII mode pin mux settings */
+       for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+       for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+       for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+       for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+       for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+#endif
 
 #ifdef CONFIG_RGMII
        return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
+#elif defined CONFIG_GMII
+       return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
 #else
        return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
 #endif

diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index 40eabce..ac3cd36 100644 (file)
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -1,5 +1,5 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
 CONFIG_FDTFILE="sun6i-a31-m9.dtb"
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_SUNXI=y