}
static bool
-iris_bufmgr_query_meminfo(struct iris_bufmgr *bufmgr)
-{
- struct drm_i915_query_memory_regions *meminfo =
- intel_i915_query_alloc(bufmgr->fd, DRM_I915_QUERY_MEMORY_REGIONS, NULL);
- if (meminfo == NULL)
- return false;
-
- for (int i = 0; i < meminfo->num_regions; i++) {
- const struct drm_i915_memory_region_info *mem = &meminfo->regions[i];
- switch (mem->region.memory_class) {
- case I915_MEMORY_CLASS_SYSTEM:
- bufmgr->sys.region = mem->region;
- bufmgr->sys.size = mem->probed_size;
- break;
- case I915_MEMORY_CLASS_DEVICE:
- bufmgr->vram.region = mem->region;
- bufmgr->vram.size = mem->probed_size;
- break;
- default:
- break;
- }
- }
+iris_bufmgr_get_meminfo(struct iris_bufmgr *bufmgr,
+ struct intel_device_info *devinfo)
+{
+ bufmgr->sys.region.memory_class = devinfo->mem.sram.mem_class;
+ bufmgr->sys.region.memory_instance = devinfo->mem.sram.mem_instance;
+ bufmgr->sys.size = devinfo->mem.sram.mappable.size;
- free(meminfo);
+ bufmgr->vram.region.memory_class = devinfo->mem.vram.mem_class;
+ bufmgr->vram.region.memory_instance = devinfo->mem.vram.mem_instance;
+ bufmgr->vram.size = devinfo->mem.vram.mappable.size;
return true;
}
bufmgr->has_mmap_offset = gem_param(fd, I915_PARAM_MMAP_GTT_VERSION) >= 4;
bufmgr->has_userptr_probe =
gem_param(fd, I915_PARAM_HAS_USERPTR_PROBE) >= 1;
- iris_bufmgr_query_meminfo(bufmgr);
+ iris_bufmgr_get_meminfo(bufmgr, devinfo);
STATIC_ASSERT(IRIS_MEMZONE_SHADER_START == 0ull);
const uint64_t _4GB = 1ull << 32;
{
uint64_t vram = iris_bufmgr_vram_size(screen->bufmgr);
uint64_t sram = iris_bufmgr_sram_size(screen->bufmgr);
- uint64_t osmem;
if (vram) {
return vram / (1024 * 1024);
} else if (sram) {
return sram / (1024 * 1024);
- } else if (os_get_available_system_memory(&osmem)) {
- return osmem / (1024 * 1024);
} else {
/* This is the old code path, it get the GGTT size from the kernel
* (which should always be 4Gb on Gfx8+).