Revert "drm/amd/display: Refactor and add visual confirm for HW Flip Queue"

This reverts commit 3ca402375a2197579d1029e7fa9d856847fe0e7b.

Recent visual confirm changes are regressing the driver, causing a
black screen on boot in some green sardine configs, or visual confirm
is not updated at all.

Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 81803463ca9bcf3a761bbfb48de83d00b772879b..8f11e2b58cd725de5502284819df2429fcb3751e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2502,25 +2502,9 @@ static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state
                dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
 }
 
-void dcn10_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)
-{
-       struct dce_hwseq *hws = dc->hwseq;
-       struct mpc *mpc = dc->res_pool->mpc;
-
-       if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
-               hws->funcs.get_hdr_visual_confirm_color(pipe_ctx, color);
-       else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
-               hws->funcs.get_surface_visual_confirm_color(pipe_ctx, color);
-       else
-               color_space_to_black_color(
-                               dc, pipe_ctx->stream->output_color_space, color);
-
-       if (mpc->funcs->set_bg_color)
-               mpc->funcs->set_bg_color(mpc, color, mpcc_id);
-}
-
 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
+       struct dce_hwseq *hws = dc->hwseq;
        struct hubp *hubp = pipe_ctx->plane_res.hubp;
        struct mpcc_blnd_cfg blnd_cfg = {{0}};
        bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
@@ -2529,6 +2513,18 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
        struct mpc *mpc = dc->res_pool->mpc;
        struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
 
+       if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
+               hws->funcs.get_hdr_visual_confirm_color(
+                               pipe_ctx, &blnd_cfg.black_color);
+       } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
+               hws->funcs.get_surface_visual_confirm_color(
+                               pipe_ctx, &blnd_cfg.black_color);
+       } else {
+               color_space_to_black_color(
+                               dc, pipe_ctx->stream->output_color_space,
+                               &blnd_cfg.black_color);
+       }
+
        if (per_pixel_alpha)
                blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
        else
@@ -2560,8 +2556,6 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
         */
        mpcc_id = hubp->inst;
 
-       dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
-
        /* If there is no full update, don't need to touch MPC tree*/
        if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
                mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index 478180b96d8d837d8cc9453a853f7701ec2f851b..c9bdffe5989bc0e6552392b9fcb70d8f3dba68df 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -206,10 +206,4 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc);
 
 void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits);
 
-void dcn10_update_visual_confirm_color(
-               struct dc *dc,
-               struct pipe_ctx *pipe_ctx,
-               struct tg_color *color,
-               int mpcc_id);
-
 #endif /* __DC_HWSS_DCN10_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
index 4ff3ebc25438cf9bb265ee471908badc90c73cc5..680ca53455a2e2cf127fb0e4b746128bf4102023 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
@@ -82,7 +82,6 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
        .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
        .set_pipe = dce110_set_pipe,
        .get_dcc_en_bits = dcn10_get_dcc_en_bits,
-       .update_visual_confirm_color = dcn10_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn10_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index da74269feb755b93f007cb730bbda1ef403dc3fd..b096011acb490fff2016c154c2ccd20f723b0479 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -64,8 +64,6 @@ void mpc1_set_bg_color(struct mpc *mpc,
                        MPCC_BG_G_Y, bg_g_y);
        REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0,
                        MPCC_BG_B_CB, bg_b_cb);
-
-       bottommost_mpcc->blnd_cfg.black_color = *bg_color;
 }
 
 static void mpc1_update_blending(
@@ -248,8 +246,6 @@ struct mpcc *mpc1_insert_plane(
                }
        }
 
-       mpc->funcs->set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id);
-
        /* update the blending configuration */
        mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);
 
@@ -499,7 +495,6 @@ static const struct mpc_funcs dcn10_mpc_funcs = {
        .set_output_csc = NULL,
        .set_output_gamma = NULL,
        .get_mpc_out_mux = mpc1_get_mpc_out_mux,
-       .set_bg_color = mpc1_set_bg_color,
 };
 
 void dcn10_mpc_construct(struct dcn10_mpc *mpc10,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 25de151588014076368d937b0dc0eaecd7429939..484a30592987f26733ffc2466227cbcaa20472d6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2267,25 +2267,9 @@ void dcn20_get_mpctree_visual_confirm_color(
        *color = pipe_colors[top_pipe->pipe_idx];
 }
 
-void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)
-{
-       struct dce_hwseq *hws = dc->hwseq;
-       struct mpc *mpc = dc->res_pool->mpc;
-
-       /* input to MPCC is always RGB, by default leave black_color at 0 */
-       if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
-               hws->funcs.get_hdr_visual_confirm_color(pipe_ctx, color);
-       else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
-               hws->funcs.get_surface_visual_confirm_color(pipe_ctx, color);
-       else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
-               dcn20_get_mpctree_visual_confirm_color(pipe_ctx, color);
-
-       if (mpc->funcs->set_bg_color)
-               mpc->funcs->set_bg_color(mpc, color, mpcc_id);
-}
-
 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
+       struct dce_hwseq *hws = dc->hwseq;
        struct hubp *hubp = pipe_ctx->plane_res.hubp;
        struct mpcc_blnd_cfg blnd_cfg = { {0} };
        bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
@@ -2294,6 +2278,15 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
        struct mpc *mpc = dc->res_pool->mpc;
        struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
 
+       // input to MPCC is always RGB, by default leave black_color at 0
+       if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
+               hws->funcs.get_hdr_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);
+       } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
+               hws->funcs.get_surface_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);
+       } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
+               dcn20_get_mpctree_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);
+       }
+
        if (per_pixel_alpha)
                blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
        else
@@ -2327,8 +2320,6 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
         */
        mpcc_id = hubp->inst;
 
-       dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
-
        /* If there is no full update, don't need to touch MPC tree*/
        if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
                !pipe_ctx->update_flags.bits.mpcc) {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
index 6bba191cd33e3a34a3bb6f86da020ac096a17b46..c69f766a40ceb99143ca0482b26bc4ed2154cc61 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
@@ -146,10 +146,5 @@ void dcn20_set_disp_pattern_generator(const struct dc *dc,
                const struct tg_color *solid_color,
                int width, int height, int offset);
 
-void dcn20_update_visual_confirm_color(struct dc *dc,
-               struct pipe_ctx *pipe_ctx,
-               struct tg_color *color,
-               int mpcc_id);
-
 #endif /* __DC_HWSS_DCN20_H__ */
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
index 2f59f10e5f09416b14139475b0ec5b161adbfd29..b5bb613eed4d086a9977f13b15e0386bd7d5c284 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
@@ -96,7 +96,6 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
 #endif
        .set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
        .get_dcc_en_bits = dcn10_get_dcc_en_bits,
-       .update_visual_confirm_color = dcn20_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn20_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
index 947eb0df3f125b99d0bdc906c51e90e33f8ba1a2..6a99fdd55e8c154c835cb7fe4a86c6f6d6d52721 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
@@ -67,6 +67,7 @@ void mpc2_update_blending(
        REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain);
        REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain);
 
+       mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id);
        mpcc->blnd_cfg = *blnd_cfg;
 }
 
@@ -556,7 +557,6 @@ const struct mpc_funcs dcn20_mpc_funcs = {
        .set_output_gamma = mpc2_set_output_gamma,
        .power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut,
        .get_mpc_out_mux = mpc1_get_mpc_out_mux,
-       .set_bg_color = mpc1_set_bg_color,
 };
 
 void dcn20_mpc_construct(struct dcn20_mpc *mpc20,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
index 523e25f7e4103df22e9d483203dd71f93fb0f589..4f20a85ff39689fa52baa4f8e31de6279853ba38 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
@@ -100,7 +100,6 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
        .is_abm_supported = dcn21_is_abm_supported,
        .set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
        .get_dcc_en_bits = dcn10_get_dcc_en_bits,
-       .update_visual_confirm_color = dcn20_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn21_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index a978d848d370ecaebc1ee20fc669f7b4eba5e251..bf7fa98b39eb2e3426ab7b3b58cbd10a26387004 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -99,7 +99,6 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
        .set_pipe = dcn21_set_pipe,
        .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
        .get_dcc_en_bits = dcn10_get_dcc_en_bits,
-       .update_visual_confirm_color = dcn20_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn30_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
index a82319f4d081d42ba66f19ce903bab65dbe4ca1c..950c9bfd53de516038648cb4a1df8169d1390d40 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
@@ -1431,7 +1431,7 @@ const struct mpc_funcs dcn30_mpc_funcs = {
        .release_rmu = mpcc3_release_rmu,
        .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut,
        .get_mpc_out_mux = mpc1_get_mpc_out_mux,
-       .set_bg_color = mpc1_set_bg_color,
+
 };
 
 void dcn30_mpc_construct(struct dcn30_mpc *mpc30,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
index 181f2175ac955a44e624ade6bb9ca41491c62c61..70b053d9ba405e2862f11f7d0dd22c70ce33d022 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
@@ -101,7 +101,6 @@ static const struct hw_sequencer_funcs dcn301_funcs = {
        .get_dcc_en_bits = dcn10_get_dcc_en_bits,
        .optimize_pwr_state = dcn21_optimize_pwr_state,
        .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
-       .update_visual_confirm_color = dcn20_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn301_private_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index 640bb432bd6abf5818410f63275f6287b7965f89..75c77ad9cbfee89200c161983d3b76e27cb72951 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -363,9 +363,6 @@ struct mpc_funcs {
                        struct mpc *mpc,
                        int opp_id);
 
-       void (*set_bg_color)(struct mpc *mpc,
-                       struct tg_color *bg_color,
-                       int mpcc_id);
 };
 
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 43284d410687938f89c3584bb2a46e2793a568c2..1d5853c95448d553b2128fe42df9a89ef5e08985 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -235,10 +235,6 @@ struct hw_sequencer_funcs {
                        enum dc_color_depth color_depth,
                        const struct tg_color *solid_color,
                        int width, int height, int offset);
-       void (*update_visual_confirm_color)(struct dc *dc,
-                       struct pipe_ctx *pipe_ctx,
-                       struct tg_color *color,
-                       int mpcc_id);
 };
 
 void color_space_to_black_color(