i.MX7ULP: Workaround APLL PFD2 to 345.6Mhz

The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider
set to 1. This frequecy is out of ULP A0 spec. The MAX rate for GPU
is 350Mhz. So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28)
to workaround the problem. The correct fix should let GPU handle the
clock rate in kernel.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c
index e333c78..7012157 100644 (file)
--- a/arch/arm/mach-imx/mx7ulp/clock.c
+++ b/arch/arm/mach-imx/mx7ulp/clock.c
@@ -300,9 +300,9 @@ void clock_init(void)
 
        scg_a7_soscdiv_init();
 
-       /* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */
+       /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */
        scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
-       scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 20);
+       scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28);
        scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
 
        init_clk_lpuart();