drm/amd/display: dce_dmcu: add DCE6 specific macros,functions

[Why]
DCE6 has no SMU_INTERRUPT_CONTROL register, but it's used for DCN10 and later

[How]
Add DCE6 specific macros definitions for DMCU registers and masks
DCE6 DMCU macros will avoid buiding errors when using DCE6 headers
There is no other change needed in dce_dcmu

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
index 5e044c2d3d6d31f001f42648025b689fdc4270cc..93e7f34d4775e164c02db133233790b9cba2487d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
@@ -46,6 +46,24 @@
        SR(SMU_INTERRUPT_CONTROL), \
        SR(DC_DMCU_SCRATCH)
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#define DMCU_DCE60_REG_LIST() \
+       SR(DMCU_CTRL), \
+       SR(DMCU_STATUS), \
+       SR(DMCU_RAM_ACCESS_CTRL), \
+       SR(DMCU_IRAM_WR_CTRL), \
+       SR(DMCU_IRAM_WR_DATA), \
+       SR(MASTER_COMM_DATA_REG1), \
+       SR(MASTER_COMM_DATA_REG2), \
+       SR(MASTER_COMM_DATA_REG3), \
+       SR(MASTER_COMM_CMD_REG), \
+       SR(MASTER_COMM_CNTL_REG), \
+       SR(DMCU_IRAM_RD_CTRL), \
+       SR(DMCU_IRAM_RD_DATA), \
+       SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
+       SR(DC_DMCU_SCRATCH)
+#endif
+
 #define DMCU_DCE80_REG_LIST() \
        SR(DMCU_CTRL), \
        SR(DMCU_STATUS), \
@@ -104,6 +122,25 @@
                        STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \
        DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
 
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#define DMCU_MASK_SH_LIST_DCE60(mask_sh) \
+       DMCU_SF(DMCU_CTRL, \
+                       DMCU_ENABLE, mask_sh), \
+       DMCU_SF(DMCU_STATUS, \
+                       UC_IN_STOP_MODE, mask_sh), \
+       DMCU_SF(DMCU_STATUS, \
+                       UC_IN_RESET, mask_sh), \
+       DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
+                       IRAM_HOST_ACCESS_EN, mask_sh), \
+       DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
+                       IRAM_WR_ADDR_AUTO_INC, mask_sh), \
+       DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
+                       IRAM_RD_ADDR_AUTO_INC, mask_sh), \
+       DMCU_SF(MASTER_COMM_CMD_REG, \
+                       MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
+       DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
+#endif
+
 #define DMCU_MASK_SH_LIST_DCE80(mask_sh) \
        DMCU_SF(DMCU_CTRL, \
                        DMCU_ENABLE, mask_sh), \