lcd: update phy disable setting for tl1 [1/1]

PD#SWPL-2399

Problem:
Power consumption for tl1 lcd suspend need improved

Solution:
shutdown tl1 phy when lcd disable

Verify:
skt x309

Change-Id: Ibce3539c5193b1f9347ff71882bab2604666a76e
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>

diff --git a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c
index c35ed79..6076d79 100644 (file)
--- a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c
@@ -2336,6 +2336,9 @@ void lcd_clk_disable(void)
                if (table[i].flag == LCD_CLK_CTRL_EN) {
                        lcd_hiu_setb(table[i].reg, 0,
                                table[i].bit, table[i].len);
+               } else if (table[i].flag == LCD_CLK_CTRL_RST) {
+                       lcd_hiu_setb(table[i].reg, 1,
+                               table[i].bit, table[i].len);
                }
                i++;
        }

diff --git a/drivers/amlogic/media/vout/lcd/lcd_reg.h b/drivers/amlogic/media/vout/lcd/lcd_reg.h
index c622569..5a5cd15 100644 (file)
--- a/drivers/amlogic/media/vout/lcd/lcd_reg.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_reg.h
@@ -855,7 +855,9 @@
 #define VBO_TMCHK_VDE_STATE_H                      0x14f7
 #define VBO_INTR_STATE                             0x14f8
 #define VBO_INFILTER_CTRL                          0x14f9
+#define VBO_INFILTER_TICK_PERIOD_L                 0x14f9
 #define VBO_INSGN_CTRL                             0x14fa
+#define VBO_INFILTER_TICK_PERIOD_H                 0x1477
 
 /* ********************************
  * Video Interface:  VENC_VCBUS_BASE = 0x1b

diff --git a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
index d072b0d..4c576bd 100644 (file)
--- a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
@@ -134,9 +134,30 @@ static void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status)
                        break;
                }
        } else {
-               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
-               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
-               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0);
+               switch (lcd_drv->data->chip_type) {
+               case LCD_CHIP_TL1:
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8,  0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1,  0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9,  0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2,  0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3,  0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4,  0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6,  0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7,  0);
+                       break;
+               default:
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0);
+                       break;
+               }
        }
 }
 
@@ -208,9 +229,30 @@ static void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status)
                        break;
                }
        } else {
-               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
-               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
-               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0);
+               switch (lcd_drv->data->chip_type) {
+               case LCD_CHIP_TL1:
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8,  0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1,  0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9,  0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2,  0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3,  0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4,  0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6,  0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7,  0);
+                       break;
+               default:
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
+                       lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0);
+                       break;
+               }
        }
 }
 
@@ -276,9 +318,21 @@ static void lcd_p2p_phy_set(struct lcd_config_s *pconf, int status)
                lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
                lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0x06020602);
        } else {
-               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
-               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
-               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0);
+               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0);
+               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
+               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0);
+               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8,  0);
+               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1,  0);
+               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9,  0);
+               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2,  0);
+               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
+               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3,  0);
+               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
+               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4,  0);
+               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
+               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6,  0);
+               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
+               lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7,  0);
        }
 }
 
@@ -809,6 +863,7 @@ static void lcd_vbyone_cdr_training_hold(struct vbyone_config_s *vx1_conf,
 
 static void lcd_vbyone_control_set(struct lcd_config_s *pconf)
 {
+       struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
        int lane_count, byte_mode, region_num, hsize, vsize, color_fmt;
        int vin_color, vin_bpp;
 
@@ -890,7 +945,17 @@ static void lcd_vbyone_control_set(struct lcd_config_s *pconf)
        /* Mux pads in combo-phy: 0 for dsi; 1 for lvds or vbyone; 2 for edp */
        /*lcd_hiu_write(HHI_DSI_LVDS_EDP_CNTL0, 0x1);*/
 
-       lcd_vcbus_write(VBO_INFILTER_CTRL, 0xff77);
+       switch (lcd_drv->data->chip_type) {
+       case LCD_CHIP_TL1:
+               lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_L, 0xff);
+               lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_H, 0x0);
+               lcd_vcbus_setb(VBO_INSGN_CTRL, 0x7, 8, 4);
+               lcd_vcbus_setb(VBO_INSGN_CTRL, 0x7, 12, 4);
+               break;
+       default:
+               lcd_vcbus_write(VBO_INFILTER_CTRL, 0xff77);
+               break;
+       }
        lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 2, 2);
        lcd_vcbus_setb(VBO_CTRL_L, 1, 0, 1);