#ifdef CONFIG_SPL_RISCV_MMODE
#ifdef CONFIG_TARGET_LIGHT_C910
asm volatile (
- "li x29, 0x11ff\n\t"
- "csrw 0x7c1, x29\n\t"
+ "csrr x29, 0x7c1\n\t"
+ "ori x28, x29, 0x2\n\t"
+ "csrw 0x7c1, x28\n\t"
);
#endif
#endif
_start:
#if (defined CONFIG_SPL_BUILD) && (defined CONFIG_TARGET_LIGHT_C910)
+ /* Disable indirect branch prediction once entering into uboot world */
+ li t0, 0x117f
+ csrw 0x7c1, t0
+ /* Disable fence broadcase and HW TLB */
+ li t0, 0x66e30c
+ csrw 0x7c5, t0
/* Enable cache ASAP as LIGHT's requirement */
jal icache_enable
jal dcache_enable
config LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF
bool "light ant ref security boot with verification"
+config LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
+ bool "light lpi4a security boot with verification"
+
config TARGET_LIGHT_FPGA_FM_C910
bool "light fullmask FPGA board"
default n
config SPL_TEXT_BASE
hex
- default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF
- default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
+ default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A
+ default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF || LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
config SPL_MAX_SIZE
hex
(void *)LIGHT_GPIO3_BADDR);
writel(readl((void *)LIGHT_GPIO1_BADDR) & ~LIGHT_GPIO1_13,
(void *)LIGHT_GPIO1_BADDR);
+ wmb();
/* At least 10ms */
- mdelay(12);
+ mdelay(50);
writel(readl((void *)LIGHT_GPIO3_BADDR) | LIGHT_GPIO3_21,
(void *)LIGHT_GPIO3_BADDR);
writel(readl((void *)LIGHT_GPIO1_BADDR) | LIGHT_GPIO1_13,
(void *)LIGHT_GPIO1_BADDR);
+ wmb();
}
static void gmac_glue_init(uint64_t apb3s_baddr)
return CMD_RET_FAILURE;
}
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
/* Secure function for image verificaiton here */
int get_image_version(unsigned long img_src_addr)
{
/* The boards other than the LightA board perform the bus down-speed operation */
-#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined (CONFIG_TARGET_LIGHT_FM_C910_LPI4A)
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
/* axi_sram_clk: 812.8512MHz -> 688.128MHz */
tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x104);
tmp |= 0x2000;
#endif
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
extern int light_secboot(int argc, char * const argv[]);
+#endif
int do_secboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+#if CONFIG_IS_ENABLED(LIGHT_SEC_UPGRADE)
if (light_secboot(argc, argv) != 0) {
run_command("reset", 0);
return -1;
}
-
+#endif
return 0;
}
U_BOOT_CMD(
}
extern volatile uint32_t DELAY_LANE;
+extern volatile int manual_set_delay ;
static int do_mmc_set_delay_lane(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
mmc = find_mmc_device(curr_device);
if (!mmc) {
printf("no mmc device at slot %x\n", curr_device);
- return CMD_RET_FAILURE;
+ goto RET_FAILURE;
}
-
+ manual_set_delay = 1;
if (0 != snps_mmc_init(mmc))
- return CMD_RET_FAILURE;
+ goto RET_FAILURE;
mmc = init_mmc_device(curr_device, true);
if (!mmc)
- return CMD_RET_FAILURE;
-
+ goto RET_FAILURE;
+
+ manual_set_delay = 0;
return CMD_RET_SUCCESS;
+
+RET_FAILURE:
+ manual_set_delay = 0;
+ return CMD_RET_FAILURE;
}
static int do_mmc_turning(cmd_tbl_t *cmdtp, int flag,
{
struct mmc *mmc;
int i = 0, n;
+ int stop_on_ok = 1;
+ if(argc > 1 && (!strncmp(argv[1],"cont",4))){
+ stop_on_ok = 0;
+ }
for(i = 0; i <= 128; i++) {
DELAY_LANE = i;
printf("set DELAY_LANE = %d\n", DELAY_LANE);
return CMD_RET_FAILURE;
}
+ manual_set_delay = 1;
if (0 != snps_mmc_init(mmc)) {
printf("Error: mmc init error!\n");
+ manual_set_delay = 0;
return CMD_RET_FAILURE;
}
if (mmc_getwp(mmc) == 1) {
printf("Error: card is write protected!\n");
+ manual_set_delay = 0;
return CMD_RET_FAILURE;
}
n = blk_dwrite(mmc_get_blk_desc(mmc), 0, 1, 0);
if (n == 1) {
printf("blocks written: %s\n", "OK" );
- return CMD_RET_SUCCESS;
+ manual_set_delay = 0;
+ if(stop_on_ok)
+ return CMD_RET_SUCCESS;
} else {
printf("written: %s\n", "error");
}
}
-
+ manual_set_delay = 0;
if (i > 128) {
return CMD_RET_FAILURE;
}
#endif
"mmc erase blk# cnt\n"
"mmc rescan\n"
- "mmc set_delay # val\n"
- "mmc turning\n"
- "mmc memset addr # lenght\n"
+ "mmc set_delay # val - set clk out delay mannaul,reinit host and rescan dev\n"
+ "mmc turning [continue] - loop test for clk delay form 0 to 128, reinit host and rescan dev\n"
+ " - without arg [continue] exit once init and write ok\n"
+ "mmc memset addr # length - set mem addr 0xff with length '# length' \n"
"mmc part - lists available partition on current mmc device\n"
"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
"mmc list - lists available devices\n"
CONFIG_DM_PCA953X=y
CONFIG_VIDEO_VS_DPU=y
CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
CONFIG_VIDEO_DW_DSI_LIGHT=y
CONFIG_VIDEO_DW_DPHY=y
CONFIG_VIDEO_DW_DSI_HOST=y
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_LPI4A=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_DUALRANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-lpi4a"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_LPI4A=y
+CONFIG_LIGHT_SEC_UPGRADE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_LCD_CUSTOM_LOGO=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
#define HS400_DELAY_LANE 24
volatile int DELAY_LANE = 50;
+volatile int manual_set_delay = 0; //flag for cmd manual setted DELAY_LANE,non-zero is setted. auto clear in cmd
static void sdhci_phy_1_8v_init_no_pull(struct sdhci_host *host)
{
{
struct mmc *mmc = (struct mmc *)host->mmc;
u32 reg;
-
+ int restore_delay;
reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
reg &= ~SDHCI_CTRL_UHS_MASK;
-
+
+ if(manual_set_delay){
+ DELAY_LANE = DELAY_LANE & 0x7f; /*limit bit[0:6]*/
+ printf("%s: manual set delay (%d) active \n",host->name,DELAY_LANE);
+ }
switch (mmc->selected_mode) {
case UHS_SDR50:
case MMC_HS_52:
reg |= SDHCI_CTRL_UHS_SDR104;
break;
case MMC_HS_400:
- DELAY_LANE = HS400_DELAY_LANE;
+ restore_delay = DELAY_LANE;
+ if(!manual_set_delay){ /*default not set manual in cmd,when set in cmd,use DELAY_LANE set in cmd*/
+ DELAY_LANE = HS400_DELAY_LANE;
+ }
sdhci_phy_1_8v_init(host);
reg |= SNPS_SDHCI_CTRL_HS400;
+ DELAY_LANE = restore_delay; /*restore for other modes*/
break;
default:
sdhci_phy_3_3v_init(host);
ret = max_clk;
goto err;
}
-
+ //get Maximum Base Clock frequency from dts clock-frequency
+ if(0 == dev_read_u32(dev, "clock-frequency", &max_clk)){
+ host->max_clk = max_clk;
+ }
host->mmc = &plat->mmc;
host->mmc->dev = dev;
host->mmc->priv = host;
{
struct phy_device *phydev;
int phy_addr = -1, ret;
-
+
#ifdef CONFIG_PHY_ADDR
phy_addr = CONFIG_PHY_ADDR;
#endif
err = ret;
goto mdio_err;
}
-
+#ifdef GMAC_USE_FIRST_MII_BUS
if (!g_mii_bus) {
priv->bus = miiphy_get_dev_by_name(dev->name);
g_mii_bus = priv->bus;
} else {
priv->bus = g_mii_bus;
}
+#else
+ priv->bus = miiphy_get_dev_by_name(dev->name);
+#endif
ret = dw_phy_init(priv, dev);
debug("%s, ret=%d\n", __func__, ret);
if (!ret)
/* continue here for cleanup if no PHY found */
err = ret;
+#ifdef GMAC_USE_FIRST_MII_BUS
+ struct mii_dev *t_mii = NULL;
+ t_mii = miiphy_get_dev_by_name(dev->name);
+ if((g_mii_bus != t_mii) && (t_mii != NULL) ){
+ printf("free mdio bus %s\n",t_mii->name);
+ mdio_unregister(t_mii);
+ mdio_free(t_mii);
+ }
+#else
mdio_unregister(priv->bus);
mdio_free(priv->bus);
+#endif
mdio_err:
#ifdef CONFIG_CLK
Say Y here if you want to enable support for ILITEK ILI9881C
800x1280 DSI video mode panel.
+config VIDEO_LCD_CUSTOM_LOGO
+ bool "LCD CUSTOM logo support"
+ help
+ Say Y here if you want to enable support for custom logo.
+
config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
#define CONFIG_RGMII 1
#define CONFIG_PHY_MARVELL 1
#define CONFIG_NET_RETRY_COUNT 20
+#define GMAC_USE_FIRST_MII_BUS
#define CONFIG_SYS_FLASH_BASE 0x0
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define THEAD_LIGHT_FASTBOOT 1
#define LIGHT_FW_ADDR 0x0
#define LIGHT_KERNEL_ADDR 0x200000
-#define LIGHT_DTB_ADDR 0x1f00000
+#define LIGHT_DTB_ADDR 0x2400000
#define LIGHT_ROOTFS_ADDR 0x2000000
#define LIGHT_AON_FW_ADDR 0xffffef8000
#define LIGHT_TEE_FW_ADDR 0x1c000000
#define LIGHT_TF_FW_ADDR LIGHT_FW_ADDR
#define LIGHT_TF_FW_TMP_ADDR 0x100000
#define LIGHT_KERNEL_ADDR_CMD "0x200000"
-#define LIGHT_DTB_ADDR_CMD "0x1f00000"
+#define LIGHT_DTB_ADDR_CMD "0x2400000"
/* trust image name string */
/* List of different env in debug/release version */
#if defined (U_BUILD_DEBUG)
#define ENV_KERNEL_LOGLEVEL "kernel_loglevel=7\0"
-#define ENV_STR_BOOT_DELAY
+#define ENV_STR_BOOT_DELAY
#else
#define ENV_KERNEL_LOGLEVEL "kernel_loglevel=4\0"
#define ENV_STR_BOOT_DELAY "bootdelay=0\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"scriptaddr=0x00500000\0" \
"pxefile_addr_r=0x00600000\0" \
- "fdt_addr_r=0x01f00000\0" \
+ "fdt_addr_r=0x02400000\0" \
"kernel_addr_r=0x00200000\0" \
"ramdisk_addr_r=0x06000000\0" \
"boot_conf_addr_r=0xc0000000\0" \
"splashpos=m,m\0" \
"fdt_high=0xffffffffffffffff\0" \
"kernel_addr_r=0x00200000\0" \
- "kdump_buf=500M\0" \
+ "kdump_buf=180M\0" \
"mmcdev=0\0" \
"mmcbootpart=2\0" \
"boot_conf_file=/extlinux/extlinux.conf\0" \
#!/bin/sh
-make ARCH=riscv CROSS_COMPILE=~/toolchain/riscv-linux/bin/riscv64-unknown-linux-gnu- -j
+make ARCH=riscv CROSS_COMPILE=~/toolchain/riscv-linux/bin/riscv64-unknown-linux-gnu- -j BUILD_TYPE=RELEASE
LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_DATA_H)
# Generic logo
+ifeq ($(CONFIG_VIDEO_LCD_CUSTOM_LOGO),y)
+LOGO_BMP= $(srctree)/$(src)/logos/custom.bmp
+else
+
ifeq ($(LOGO_BMP),)
LOGO_BMP= $(srctree)/$(src)/logos/denx.bmp
endif # !LOGO_BMP
+endif
+
#
# Use native tools and options
# Define __KERNEL_STRICT_NAMES to prevent typedef overlaps
projects / platform / kernel / u-boot-thead.git / commitdiff