}
}
-static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx, LLVMValueRef src0)
-{
- src0 = ac_to_float(ctx, src0);
- LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(src0));
- return LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, zero, "");
-}
-
static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx, LLVMValueRef src0, unsigned bitsize)
{
switch (bitsize) {
case nir_op_b2f64:
result = emit_b2f(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
break;
- case nir_op_f2b1:
- result = emit_f2b(&ctx->ac, src[0]);
- break;
case nir_op_b2i8:
case nir_op_b2i16:
case nir_op_b2i32:
else
return agx_not_to(b, dst, s0);
- case nir_op_f2b1:
- return agx_fcmpsel_to(b, dst, s0, i0, i0, i1, AGX_FCOND_EQ);
case nir_op_b2b1:
return agx_icmpsel_to(b, dst, s0, i0, i0, i1, AGX_ICOND_UEQ);
vir_set_pf(c, vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
break;
- case nir_op_f2b32:
- vir_set_pf(c, vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
- cond_invert = true;
- break;
-
default:
return false;
}
break;
}
- case nir_op_f2b32:
case nir_op_feq32:
case nir_op_fneu32:
case nir_op_fge32:
return __packFloat64(zSign, 0x412 - shiftCount, zFrac0, zFrac1);
}
-bool
-__fp64_to_bool(uint64_t a)
-{
- return !__feq64_nonnan(__fabs64(a), 0ul);
-}
-
uint64_t
__bool_to_fp64(bool a)
{
CASE_ALL_SIZES(nir_op_uge)
CASE_ALL_SIZES(nir_op_ieq)
CASE_ALL_SIZES(nir_op_ine)
- case nir_op_f2b1:
- case nir_op_f2b8:
- case nir_op_f2b16:
- case nir_op_f2b32:
case nir_op_inot:
return true;
default:
stripped = opcode.rstrip('0123456789')
if stripped in conv_opcode_types:
# Matches that use conversion opcodes with a specific type,
- # like f2b1, are tricky. Either we construct the automaton to
- # match specific NIR opcodes like nir_op_f2b1, in which case we
+ # like f2i1, are tricky. Either we construct the automaton to
+ # match specific NIR opcodes like nir_op_f2i1, in which case we
# need to create separate items for each possible NIR opcode
- # for patterns that have a generic opcode like f2b, or we
+ # for patterns that have a generic opcode like f2i, or we
# construct it to match the search opcode, in which case we
- # need to map f2b1 to f2b when constructing the automaton. Here
+ # need to map f2i1 to f2i when constructing the automaton. Here
# we do the latter.
opcode = stripped
self.opcodes.add(opcode)
/* Nothing to do here, we do not specialize these opcodes by bit-size */
break;
- case nir_op_f2b1:
- opcode = bit_size == 8 ? nir_op_f2b8 :
- bit_size == 16 ? nir_op_f2b16 : nir_op_f2b32;
- break;
-
case nir_op_b2b1:
/* Since the canonical bit size is the size of the src, it's a no-op */
opcode = nir_op_mov;
case nir_op_b2f32: alu->op = nir_op_mov; break;
case nir_op_b2i32: alu->op = nir_op_mov; break;
- case nir_op_f2b1:
- rep = nir_sne(b, nir_ssa_for_alu_src(b, alu, 0),
- nir_imm_float(b, 0));
- break;
case nir_op_b2b1: alu->op = nir_op_mov; break;
case nir_op_flt: alu->op = nir_op_slt; break;
/* These we expect to have booleans but the opcode doesn't change */
break;
- case nir_op_f2b1: alu->op = nir_op_f2b32; break;
-
case nir_op_b2b32:
case nir_op_b2b1:
/* We're mutating instructions in a dominance-preserving order so our
mangled_name = "__fp64_to_uint(u641;";
return_type = glsl_uint_type();
break;
- case nir_op_f2b1:
- case nir_op_f2b32:
- name = "__fp64_to_bool";
- mangled_name = "__fp64_to_bool(u641;";
- return_type = glsl_bool_type();
- break;
case nir_op_b2f64:
name = "__bool_to_fp64";
mangled_name = "__bool_to_fp64(b1;";
elif src_t == tuint:
dst_types = [tfloat, tuint]
elif src_t == tfloat:
- dst_types = [tint, tuint, tfloat, tbool]
+ dst_types = [tint, tuint, tfloat]
for dst_t in dst_types:
for dst_bit_size in type_sizes(dst_t):
return nir_op_mov;
}
- /* i2b and u2b do not exist. Use ine (via nir_type_conversion) instead */
- assert((src_base != nir_type_int && src_base != nir_type_uint) ||
- dst_base != nir_type_bool);
+ /* f2b, i2b, and u2b do not exist. Use ine or fne (via nir_type_conversion)
+ * instead.
+ */
+ assert(src_base == dst_base || dst_base != nir_type_bool);
switch (src_base) {
% for src_t in ['int', 'uint', 'float', 'bool']:
% else:
<% dst_t = 'int' %>
% endif
-% elif src_t in ['int', 'uint'] and dst_t == 'bool':
+% elif src_t != 'bool' and dst_t == 'bool':
<% continue %>
% endif
switch (dst_bit_size) {
(('fabs', ('u2f', a)), ('u2f', a)),
(('iabs', ('iabs', a)), ('iabs', a)),
(('iabs', ('ineg', a)), ('iabs', a)),
- (('f2b', ('fneg', a)), ('f2b', a)),
(('~fadd', a, 0.0), a),
# a+0.0 is 'a' unless 'a' is denormal or -0.0. If it's only used by a
# floating point instruction, they should flush any input denormals and we
# Conversions
(('f2i', ('ftrunc', a)), ('f2i', a)),
(('f2u', ('ftrunc', a)), ('f2u', a)),
- (('inot', ('f2b1', a)), ('feq', a, 0.0)),
# Conversions from 16 bits to 32 bits and back can always be removed
(('f2fmp', ('f2f32', 'a@16')), a),
optimizations.append((('inot', ('iand(is_used_once)', (left, a, b), (right, c, d))),
('ior', (invert[left], a, b), (invert[right], c, d))))
-# Optimize f2bN(b2f(x)) -> x
-for size in type_sizes('bool'):
- aN = 'a@' + str(size)
- f2bN = 'f2b' + str(size)
- optimizations.append(((f2bN, ('b2f', aN)), a))
-
# Optimize x2yN(b2x(x)) -> b2y
for x, y in itertools.product(['f', 'u', 'i'], ['f', 'u', 'i']):
if x != 'f' and y != 'f' and x != y:
nop == nir_op_##op##32 || \
nop == nir_op_##op##64;
-#define MATCH_BCONV_CASE(op) \
- case nir_search_op_##op: \
- return nop == nir_op_##op##1 || \
- nop == nir_op_##op##32;
-
switch (sop) {
MATCH_FCONV_CASE(i2f)
MATCH_FCONV_CASE(u2f)
MATCH_ICONV_CASE(i2i)
MATCH_FCONV_CASE(b2f)
MATCH_ICONV_CASE(b2i)
- MATCH_BCONV_CASE(f2b)
default:
unreachable("Invalid nir_search_op");
}
#undef MATCH_FCONV_CASE
#undef MATCH_ICONV_CASE
-#undef MATCH_BCONV_CASE
}
uint16_t
case nir_op_##op##64: \
return nir_search_op_##op;
-#define MATCH_BCONV_CASE(op) \
- case nir_op_##op##1: \
- case nir_op_##op##32: \
- return nir_search_op_##op;
-
switch (nop) {
MATCH_FCONV_CASE(i2f)
MATCH_ICONV_CASE(i2i)
MATCH_FCONV_CASE(b2f)
MATCH_ICONV_CASE(b2i)
- MATCH_BCONV_CASE(f2b)
default:
return nop;
}
#undef MATCH_FCONV_CASE
#undef MATCH_ICONV_CASE
-#undef MATCH_BCONV_CASE
}
static nir_op
default: unreachable("Invalid bit size"); \
}
-#define RET_BCONV_CASE(op) \
- case nir_search_op_##op: \
- switch (bit_size) { \
- case 1: return nir_op_##op##1; \
- case 32: return nir_op_##op##32; \
- default: unreachable("Invalid bit size"); \
- }
-
switch (sop) {
RET_FCONV_CASE(i2f)
RET_FCONV_CASE(u2f)
RET_ICONV_CASE(i2i)
RET_FCONV_CASE(b2f)
RET_ICONV_CASE(b2i)
- RET_BCONV_CASE(f2b)
default:
unreachable("Invalid nir_search_op");
}
#undef RET_FCONV_CASE
#undef RET_ICONV_CASE
-#undef RET_BCONV_CASE
}
static bool
switch (expr->opcode) {
#define CASE(n) \
case nir_search_op_##n: fprintf(stderr, #n); break;
- CASE(f2b)
CASE(b2f)
CASE(b2i)
CASE(i2i)
nir_search_op_i2i,
nir_search_op_b2f,
nir_search_op_b2i,
- nir_search_op_f2b,
nir_num_search_ops,
};
dst[0] = create_cov(ctx, create_cov(ctx, src[0], 32, nir_op_f2f16_rtne),
16, nir_op_f2f32);
break;
- case nir_op_f2b1:
- dst[0] = ir3_CMPS_F(
- b, src[0], 0,
- create_immed_typed(b, 0, type_float_size(bs[0])), 0);
- dst[0]->cat2.condition = IR3_COND_NE;
- break;
case nir_op_b2b1:
/* b2b1 will appear when translating from
}
static LLVMValueRef
-flt_to_bool32(struct lp_build_nir_context *bld_base,
- uint32_t src_bit_size,
- LLVMValueRef val)
-{
- LLVMBuilderRef builder = bld_base->base.gallivm->builder;
- struct lp_build_context *flt_bld = get_flt_bld(bld_base, src_bit_size);
- LLVMValueRef result =
- lp_build_cmp(flt_bld, PIPE_FUNC_NOTEQUAL, val, flt_bld->zero);
- if (src_bit_size == 64)
- result = LLVMBuildTrunc(builder, result, bld_base->int_bld.vec_type, "");
- if (src_bit_size == 16)
- result = LLVMBuildSExt(builder, result, bld_base->int_bld.vec_type, "");
- return result;
-}
-
-
-static LLVMValueRef
fcmp32(struct lp_build_nir_context *bld_base,
enum pipe_compare_func compare,
uint32_t src_bit_size,
case nir_op_bitfield_reverse:
result = lp_build_bitfield_reverse(get_int_bld(bld_base, false, src_bit_size[0]), src[0]);
break;
- case nir_op_f2b32:
- result = flt_to_bool32(bld_base, src_bit_size[0], src[0]);
- break;
case nir_op_f2f16:
if (src_bit_size[0] == 64)
src[0] = LLVMBuildFPTrunc(builder, src[0],
ntt_64bit_1f(c));
break;
- case nir_op_f2b32:
- if (src_64)
- ntt_DSNE(c, dst, src[0], ureg_imm1f(c->ureg, 0));
- else
- ntt_FSNE(c, dst, src[0], ureg_imm1f(c->ureg, 0));
- break;
-
case nir_op_b2i32:
ntt_AND(c, dst, src[0], ureg_imm1u(c->ureg, 1));
break;
UOP(f2u32, F2I, 0_X_X),
UOP(b2f32, AND, 0_X_X), /* AND with fui(1.0f) */
UOP(b2i32, AND, 0_X_X), /* AND with 1 */
- OPC(f2b32, CMP, 0_X_X, NE), /* != 0.0 */
/* arithmetic */
IOP(iadd, ADD, 0_X_1),
case nir_op_b2i32:
inst.src[2] = etna_immediate_int(1);
break;
- case nir_op_f2b32:
- inst.src[1] = etna_immediate_float(0.0f);
- break;
case nir_op_ineg:
inst.src[0] = etna_immediate_int(0);
src[0].neg = 1;
case nir_op_b32csel:
return emit_alu_op3(*alu, op3_cnde_int, shader, {0, 2, 1});
- case nir_op_f2b32:
- return emit_alu_comb_with_zero(*alu, op2_setne_dx10, shader);
case nir_op_fabs:
return emit_alu_op1(*alu, op1_mov, shader, {1 << alu_src0_abs});
case nir_op_fadd:
switch (alu->op) {
case nir_op_bcsel:
return nir_dest_bit_size(alu->dest.dest) == 64;
- case nir_op_f2b1:
case nir_op_f2i32:
case nir_op_f2u32:
case nir_op_f2i64:
nir_unpack_64_2x32_split_y(b, nir_ssa_for_alu_src(b, alu, 2)));
return nir_pack_64_2x32_split(b, lo, hi);
}
- case nir_op_f2b1: {
- auto mask = nir_component_mask(nir_dest_num_components(alu->dest.dest));
- return nir_fneu(b,
- nir_channels(b, nir_ssa_for_alu_src(b, alu, 0), mask),
- nir_imm_zero(b, nir_dest_num_components(alu->dest.dest), 64));
- }
case nir_op_f2i32: {
auto src = nir_ssa_for_alu_src(b, alu, 0);
auto gt0 = nir_flt(b, nir_imm_double(b, 0.0), src);
case nir_op_b2i32:
result = qir_AND(c, src[0], qir_uniform_ui(c, 1));
break;
- case nir_op_f2b32:
- qir_SF(c, src[0]);
- result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC,
- qir_uniform_ui(c, ~0),
- qir_uniform_ui(c, 0)));
- break;
case nir_op_iadd:
result = qir_ADD(c, src[0], src[1]);
src[0]);
break;
- case nir_op_f2b1:
- assert(nir_op_infos[alu->op].num_inputs == 1);
- result = emit_binop(ctx, SpvOpFOrdNotEqual, dest_type, src[0],
- get_fvec_constant(ctx,
- nir_src_bit_size(alu->src[0].src),
- num_components, 0));
- break;
-
#define BINOP(nir_op, spirv_op) \
case nir_op: \
inst = bld.emit(SHADER_OPCODE_RSQ, result, op[0]);
break;
- case nir_op_f2b32: {
- uint32_t bit_size = nir_src_bit_size(instr->src[0].src);
- if (bit_size == 64) {
- /* two-argument instructions can't take 64-bit immediates */
- fs_reg zero = vgrf(glsl_type::double_type);
- fs_reg tmp = vgrf(glsl_type::double_type);
-
- bld.MOV(zero, setup_imm_df(bld, 0.0));
-
- /* A SIMD16 execution needs to be split in two instructions, so use
- * a vgrf instead of the flag register as dst so instruction splitting
- * works
- */
- bld.CMP(tmp, op[0], zero, BRW_CONDITIONAL_NZ);
- bld.MOV(result, subscript(tmp, BRW_REGISTER_TYPE_UD, 0));
- } else {
- fs_reg zero;
- if (bit_size == 32) {
- zero = brw_imm_f(0.0f);
- } else {
- assert(bit_size == 16);
- zero = retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF);
- }
- bld.CMP(result, op[0], zero, BRW_CONDITIONAL_NZ);
- }
- break;
- }
-
case nir_op_ftrunc:
inst = bld.RNDZ(result, op[0]);
if (devinfo->ver < 6) {
}
break;
- case nir_op_f2b32:
- if (nir_src_bit_size(instr->src[0].src) == 64) {
- /* We use a MOV with conditional_mod to check if the provided value is
- * 0.0. We want this to flush denormalized numbers to zero, so we set a
- * source modifier on the source operand to trigger this, as source
- * modifiers don't affect the result of the testing against 0.0.
- */
- src_reg value = op[0];
- value.abs = true;
- vec4_instruction *inst = emit(MOV(dst_null_df(), value));
- inst->conditional_mod = BRW_CONDITIONAL_NZ;
-
- src_reg one = src_reg(this, glsl_type::ivec4_type);
- emit(MOV(dst_reg(one), brw_imm_d(~0)));
- inst = emit(BRW_OPCODE_SEL, dst, one, brw_imm_d(0));
- inst->predicate = BRW_PREDICATE_NORMAL;
- } else {
- emit(CMP(dst, op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ));
- }
- break;
-
case nir_op_unpack_half_2x16_split_x:
case nir_op_unpack_half_2x16_split_y:
case nir_op_pack_half_2x16_split:
lower_x2b = [
(('b2b32', 'a'), ('b2i32', 'a')),
(('b2b1', 'a'), ('ine', ('b2i32', a), 0)),
- (('f2b1', 'a'), ('fneu', a, 0)),
]
no_16bit_conv += [
}
static bool
-emit_f2b32(struct ntd_context *ctx, nir_alu_instr *alu, const struct dxil_value *val)
-{
- assert(val);
-
- const struct dxil_value *zero = dxil_module_get_float_const(&ctx->mod, 0.0f);
- return emit_cmp(ctx, alu, DXIL_FCMP_UNE, val, zero);
-}
-
-static bool
emit_f16tof32(struct ntd_context *ctx, nir_alu_instr *alu, const struct dxil_value *val, bool shift)
{
if (shift) {
case nir_op_u2u64:
return emit_cast(ctx, alu, src[0]);
- case nir_op_f2b32: return emit_f2b32(ctx, alu, src[0]);
case nir_op_b2f16: return emit_b2f16(ctx, alu, src[0]);
case nir_op_b2f32: return emit_b2f32(ctx, alu, src[0]);
case nir_op_b2f64: return emit_b2f64(ctx, alu, src[0]);
mkOp2(OP_MERGE, TYPE_U64, newDefs[0], loadImm(NULL, 0), tmp);
break;
}
- case nir_op_f2b32: {
- DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest);
- mkCmp(OP_SET, CC_NEU, TYPE_U32, newDefs[0], sTypes[0], getSrc(&insn->src[0]), zero);
- break;
- }
case nir_op_b2i8:
case nir_op_b2i16:
case nir_op_b2i32: {
BI_MUX_INT_ZERO);
break;
- case nir_op_f2b16:
- bi_mux_v2i16_to(b, dst, bi_imm_u16(0), bi_imm_u16(~0), s0,
- BI_MUX_FP_ZERO);
- break;
- case nir_op_f2b32:
- bi_mux_i32_to(b, dst, bi_imm_u32(0), bi_imm_u32(~0), s0, BI_MUX_FP_ZERO);
- break;
-
case nir_op_ieq8:
case nir_op_ine8:
case nir_op_ilt8:
ALU_CASE_CMP(b2f16, iand);
ALU_CASE_CMP(b2i32, iand);
- /* Likewise, we don't have a dedicated f2b32 instruction, but
- * we can do a "not equal to 0.0" test. */
-
- ALU_CASE_CMP(f2b32, fne);
-
ALU_CASE(frcp, frcp);
ALU_CASE(frsq, frsqrt);
ALU_CASE(fsqrt, fsqrt);