intel_mid_powerbtn: update shared SRAM address for CLV and CLVP

BZ: 30822

In CLV shared SRAM address for pb status is changed to 0xFFFF7FCB
and CLVP it is 0xFFFFEFCB.

This change is made in the SCU vA0.08

Change-Id: Ie0f824b4befc6c368d3dda6d70bcbcfda6d391c3
Signed-off-by: Renganathan, Prabu <prabu.renganathan@intel.com>
Reviewed-on: http://android.intel.com:8080/42986
Reviewed-by: Liu, Hong <hong.liu@intel.com>
Reviewed-by: Du, Alek <alek.du@intel.com>
Tested-by: Bourahmani, KarimX <karimx.bourahmani@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>

diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index e428893..1fbce34 100644 (file)
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -682,6 +682,13 @@ config INTEL_MID_POWER_BUTTON
 
          If unsure, say N.
 
+config POWER_BUTTON_CLVP
+       bool "SRAM address for CLVP"
+       depends on INTEL_MID_POWER_BUTTON
+       default n
+       ---help---
+         CLVP SRAM address for powerbutton status. Say y for CLV+ and n for CLV
+
 config INTEL_MID_OSIP
        tristate "osip driver for Intel MID platforms"
        depends on INTEL_SCU_IPC

diff --git a/drivers/platform/x86/intel_mid_powerbtn.c b/drivers/platform/x86/intel_mid_powerbtn.c
index 56b1681..cdc904e 100644 (file)
--- a/drivers/platform/x86/intel_mid_powerbtn.c
+++ b/drivers/platform/x86/intel_mid_powerbtn.c
@@ -29,8 +29,15 @@
 #define DRIVER_NAME "msic_power_btn"
 
 /* SRAM address for power button state */
+#if defined(CONFIG_BOARD_CTP) && defined(CONFIG_POWER_BUTTON_CLVP)
+#define MSIC_PB_STAT    0xffffefcb
+#elif defined(CONFIG_BOARD_CTP)
+#define MSIC_PB_STAT    0xffff7fcb
+#else
 #define MSIC_PB_STAT   0xffff7fd0
-  #define MSIC_PB_LEVEL (1 << 3) /* 1 - release, 0 - press */
+#endif
+
+#define MSIC_PB_LEVEL (1 << 3) /* 1 - release, 0 - press */
 #define MSIC_PB_LEN    1
 
 /*