drm/amd/display: Only update link settings after successful MST link train

[WHY]
Currently driver reduces verified link caps on DPIA devices if a link is
trained at a link rate below the max rate verified during link detection.
This blocks high bandwidth modes after setting a low bandwidth mode.

[HOW]
Only update link rate after a successful link train if link is MST.

Reviewed-by: Mustapha Ghaddar <Mustapha.Ghaddar@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index f72c013..e47098f 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -971,3 +971,11 @@ void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
 {
        /* TODO: add periodic detection implementation */
 }
+
+void dm_helpers_dp_mst_update_branch_bandwidth(
+               struct dc_context *ctx,
+               struct dc_link *link)
+{
+       // TODO
+}
+

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 24ed057..5304e9d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -4663,6 +4663,10 @@ void dc_link_set_preferred_training_settings(struct dc *dc,
                link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
        }
 
+       if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
+                       link->type == dc_connection_mst_branch)
+               dm_helpers_dp_mst_update_branch_bandwidth(dc->ctx, link);
+
        /* Retrain now, or wait until next stream update to apply */
        if (skip_immediate_retrain == false)
                dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index a3e1aec..b772d7f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2771,8 +2771,11 @@ bool perform_link_training_with_retries(
                                        /* Update verified link settings to current one
                                         * Because DPIA LT might fallback to lower link setting.
                                         */
-                                       link->verified_link_cap.link_rate = link->cur_link_settings.link_rate;
-                                       link->verified_link_cap.lane_count = link->cur_link_settings.lane_count;
+                                       if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+                                               link->verified_link_cap.link_rate = link->cur_link_settings.link_rate;
+                                               link->verified_link_cap.lane_count = link->cur_link_settings.lane_count;
+                                               dm_helpers_dp_mst_update_branch_bandwidth(link->ctx, link);
+                                       }
                                }
                        } else {
                                status = dc_link_dp_perform_link_training(link,

diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
index e3e5c39..af1c50e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
@@ -116,6 +116,11 @@ bool dm_helpers_dp_mst_start_top_mgr(
 bool dm_helpers_dp_mst_stop_top_mgr(
                struct dc_context *ctx,
                struct dc_link *link);
+
+void dm_helpers_dp_mst_update_branch_bandwidth(
+               struct dc_context *ctx,
+               struct dc_link *link);
+
 /**
  * OS specific aux read callback.
  */