bufmgr->has_llc = devinfo->has_llc;
bufmgr->has_tiling_uapi = devinfo->has_tiling_uapi;
bufmgr->bo_reuse = bo_reuse;
- int val;
- if (intel_gem_get_param(fd, I915_PARAM_MMAP_GTT_VERSION, &val) && val >= 4)
- bufmgr->has_mmap_offset = true;
+ bufmgr->has_mmap_offset = devinfo->has_mmap_offset;
init_cache_buckets(bufmgr);
bufmgr->has_local_mem = devinfo->has_local_mem;
bufmgr->has_tiling_uapi = devinfo->has_tiling_uapi;
bufmgr->bo_reuse = bo_reuse;
+ bufmgr->has_mmap_offset = devinfo->has_mmap_offset;
int val;
- if (intel_gem_get_param(fd, I915_PARAM_MMAP_GTT_VERSION, &val) && val >= 4)
- bufmgr->has_mmap_offset = true;
if (intel_gem_get_param(fd, I915_PARAM_HAS_USERPTR_PROBE, &val) && val >= 1)
bufmgr->has_userptr_probe = true;
iris_bufmgr_get_meminfo(bufmgr, devinfo);
update_cs_workgroup_threads(devinfo);
}
- int timestamp_frequency;
- if (getparam(fd, I915_PARAM_CS_TIMESTAMP_FREQUENCY,
- ×tamp_frequency))
- devinfo->timestamp_frequency = timestamp_frequency;
+ int val;
+ if (getparam(fd, I915_PARAM_CS_TIMESTAMP_FREQUENCY, &val))
+ devinfo->timestamp_frequency = val;
else if (devinfo->ver >= 10) {
mesa_loge("Kernel 4.15 required to read the CS timestamp frequency.");
return false;
get_context_param(fd, 0, I915_CONTEXT_PARAM_GTT_SIZE, &devinfo->gtt_size);
devinfo->has_tiling_uapi = has_get_tiling(fd);
+ if (getparam(fd, I915_PARAM_MMAP_GTT_VERSION, &val))
+ devinfo->has_mmap_offset = val >= 4;
+
return true;
}
bool has_local_mem;
bool has_lsc;
bool has_mesh_shading;
+ bool has_mmap_offset;
/**
* \name Intel hardware quirks
if (intel_gem_get_param(fd, I915_PARAM_HAS_EXEC_TIMELINE_FENCES, &val))
device->has_exec_timeline = val;
- if (intel_gem_get_param(fd, I915_PARAM_MMAP_GTT_VERSION, &val))
- device->has_mmap_offset = val >= 4;
-
if (intel_gem_get_param(fd, I915_PARAM_HAS_USERPTR_PROBE, &val))
device->has_userptr_probe = val;
/* GEM will fail to map if the offset isn't 4k-aligned. Round down. */
uint64_t map_offset;
- if (!device->physical->has_mmap_offset)
+ if (!device->physical->info.has_mmap_offset)
map_offset = offset & ~4095ull;
else
map_offset = 0;
uint64_t offset, uint64_t size, uint32_t flags)
{
void *map;
- if (device->physical->has_mmap_offset)
+ if (device->physical->info.has_mmap_offset)
map = anv_gem_mmap_offset(device, gem_handle, offset, size, flags);
else
map = anv_gem_mmap_legacy(device, gem_handle, offset, size, flags);
bool has_exec_capture;
VkQueueGlobalPriorityKHR max_context_priority;
bool has_context_isolation;
- bool has_mmap_offset;
bool has_userptr_probe;
uint64_t gtt_size;
device->always_flush_cache = INTEL_DEBUG(DEBUG_STALL) ||
driQueryOptionb(&instance->dri_options, "always_flush_cache");
- if (intel_gem_get_param(fd, I915_PARAM_MMAP_GTT_VERSION, &val))
- device->has_mmap_offset = val >= 4;
-
if (intel_gem_get_param(fd, I915_PARAM_HAS_USERPTR_PROBE, &val))
device->has_userptr_probe = val;
/* GEM will fail to map if the offset isn't 4k-aligned. Round down. */
uint64_t map_offset;
- if (!device->physical->has_mmap_offset)
+ if (!device->physical->info.has_mmap_offset)
map_offset = offset & ~4095ull;
else
map_offset = 0;
uint64_t offset, uint64_t size, uint32_t flags)
{
void *map;
- if (device->physical->has_mmap_offset)
+ if (device->physical->info.has_mmap_offset)
map = anv_gem_mmap_offset(device, gem_handle, offset, size, flags);
else
map = anv_gem_mmap_legacy(device, gem_handle, offset, size, flags);
bool has_exec_capture;
int max_context_priority;
bool has_context_isolation;
- bool has_mmap_offset;
bool has_userptr_probe;
uint64_t gtt_size;