anv: don't emit 3DSTATE_WM in pipeline batch
authorLionel Landwerlin <lionel.g.landwerlin@intel.com>
Thu, 28 Apr 2022 06:26:39 +0000 (09:26 +0300)
committerMarge Bot <emma+marge@anholt.net>
Tue, 3 May 2022 17:12:44 +0000 (17:12 +0000)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16220>

src/intel/vulkan/genX_pipeline.c
src/intel/vulkan/gfx7_cmd_buffer.c
src/intel/vulkan/gfx8_cmd_buffer.c

index 45c0c6f..d27dd05 100644 (file)
@@ -2334,20 +2334,9 @@ emit_3dstate_wm(struct anv_graphics_pipeline *pipeline,
       wm.LineStippleEnable = line && line->stippledLineEnable;
    }
 
-   uint32_t dynamic_wm_states = ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE;
-
-#if GFX_VER < 8
-   dynamic_wm_states |= ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
-#endif
-
-   if (dynamic_states & dynamic_wm_states) {
-      const struct intel_device_info *devinfo = &pipeline->base.device->info;
-      uint32_t *dws = devinfo->ver >= 8 ? pipeline->gfx8.wm : pipeline->gfx7.wm;
-      GENX(3DSTATE_WM_pack)(NULL, dws, &wm);
-   } else {
-      anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_WM), _wm)
-         _wm = wm;
-   }
+   const struct intel_device_info *devinfo = &pipeline->base.device->info;
+   uint32_t *dws = devinfo->ver >= 8 ? pipeline->gfx8.wm : pipeline->gfx7.wm;
+   GENX(3DSTATE_WM_pack)(NULL, dws, &wm);
 }
 
 static void
index 6f9d619..524b84a 100644 (file)
@@ -290,8 +290,9 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
       struct GENX(3DSTATE_WM) wm = {
          GENX(3DSTATE_WM_header),
 
-         .ThreadDispatchEnable = pipeline->force_fragment_thread_dispatch ||
-                                 !anv_cmd_buffer_all_color_write_masked(cmd_buffer),
+         .ThreadDispatchEnable = anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT) &&
+                                 (pipeline->force_fragment_thread_dispatch ||
+                                  !anv_cmd_buffer_all_color_write_masked(cmd_buffer)),
          .MultisampleRasterizationMode =
                                  genX(ms_rasterization_mode)(pipeline,
                                                              dynamic_raster_mode),
index 7d100cf..33189cc 100644 (file)
@@ -628,9 +628,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
       genX(emit_sample_pattern)(&cmd_buffer->batch, d);
 
    if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
-                                      ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
-                                      ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP)) {
-      const uint8_t color_writes = d->color_writes;
+                                      ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE)) {
       /* 3DSTATE_WM in the hope we can avoid spawning fragment shaders
        * threads.
        */
@@ -638,13 +636,20 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
       struct GENX(3DSTATE_WM) wm = {
          GENX(3DSTATE_WM_header),
 
-         .ForceThreadDispatchEnable = (pipeline->force_fragment_thread_dispatch ||
+         .ForceThreadDispatchEnable = anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT) &&
+                                      (pipeline->force_fragment_thread_dispatch ||
                                        anv_cmd_buffer_all_color_write_masked(cmd_buffer)) ?
                                       ForceON : 0,
       };
       GENX(3DSTATE_WM_pack)(NULL, wm_dwords, &wm);
 
       anv_batch_emit_merge(&cmd_buffer->batch, wm_dwords, pipeline->gfx8.wm);
+   }
+
+   if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
+                                      ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE |
+                                      ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP)) {
+      const uint8_t color_writes = d->color_writes;
 
       /* 3DSTATE_PS_BLEND to be consistent with the rest of the
        * BLEND_STATE_ENTRY.