{
#ifdef CONFIG_FSL_ESDHC
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
#else
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
#endif
#endif
return 0;
{
#ifdef CONFIG_FSL_ESDHC
#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#else
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
#endif
#endif
return 0;
#ifdef CONFIG_FSL_ESDHC
#ifdef CONFIG_FSL_USDHC
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
#else
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#endif
#else
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
#else
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#endif
#endif
#endif
/* Architecture-specific global data */
struct arch_global_data {
+#if defined(CONFIG_FSL_ESDHC)
+ u32 sdhc_clk;
+#endif
#ifdef CONFIG_AT91FAMILY
/* "static data" needed by at91's clock.c */
unsigned long cpu_clk_rate_hz;
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long fb_base; /* base address of frame buffer */
-#ifdef CONFIG_FSL_ESDHC
- unsigned long sdhc_clk;
-#endif
unsigned long relocaddr; /* Start address of U-Boot in RAM */
phys_size_t ram_size; /* RAM size */
unsigned long mon_len; /* monitor len */
gd->arch.tdm_clk = tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
- gd->sdhc_clk = sdhc_clk;
+ gd->arch.sdhc_clk = sdhc_clk;
#endif
gd->arch.core_clk = core_clk;
gd->arch.i2c1_clk = i2c1_clk;
strmhz(buf, gd->arch.tdm_clk));
#endif
#if defined(CONFIG_FSL_ESDHC)
- printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
+ printf(" SDHC: %-4s MHz\n",
+ strmhz(buf, gd->arch.sdhc_clk));
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
#if defined(CONFIG_FSL_ESDHC)
#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
defined(CONFIG_P1014)
- gd->sdhc_clk = gd->bus_clk;
+ gd->arch.sdhc_clk = gd->bus_clk;
#else
- gd->sdhc_clk = gd->bus_clk / 2;
+ gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif
#endif /* defined(CONFIG_FSL_ESDHC) */
/* Architecture-specific global data */
struct arch_global_data {
+#if defined(CONFIG_FSL_ESDHC)
+ u32 sdhc_clk;
+#endif
#if defined(CONFIG_8xx)
unsigned long brg_clk;
#endif
/* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
unsigned long pci_clk;
unsigned long mem_clk;
-#if defined(CONFIG_FSL_ESDHC)
- u32 sdhc_clk;
-#endif
phys_size_t ram_size; /* RAM size */
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
mmc->f_min = 400000;
- mmc->f_max = MIN(gd->sdhc_clk, 52000000);
+ mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);
mmc->b_max = 0;
mmc_register(mmc);
cfg = malloc(sizeof(struct fsl_esdhc_cfg));
memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
- cfg->sdhc_clk = gd->sdhc_clk;
+ cfg->sdhc_clk = gd->arch.sdhc_clk;
return fsl_esdhc_initialize(bis, cfg);
}
#endif
do_fixup_by_compat_u32(blob, compat, "clock-frequency",
- gd->sdhc_clk, 1);
+ gd->arch.sdhc_clk, 1);
do_fixup_by_compat(blob, compat, "status", "okay",
4 + 1, 1);