When the destination is a scalar and the execution width
is 1, we should use scalar vec rather.
This patch fix the following illegal instruction:
(38 ) mov(1) g124.3<1>:F acc0<8,8,1>:F
to the correct one:
(38 ) mov(1) g124.3<1>:F acc0<0,1,0>:F
Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: "Yang, Rong R" <rong.r.yang@intel.com>
sel.curr.accWrEnable = 1;
sel.MACH(GenRegister::retype(GenRegister::null(), GEN_TYPE_D), src0, src1);
sel.curr.accWrEnable = 0;
- sel.curr.execWidth = simdWidth != 1 ? 8 : 1;;
- sel.MOV(GenRegister::retype(dst, GEN_TYPE_F), GenRegister::acc());
+ if (simdWidth == 1) {
+ sel.curr.execWidth = 1;
+ sel.MOV(GenRegister::retype(dst, GEN_TYPE_F), GenRegister::vec1(GenRegister::acc()));
+ } else {
+ sel.curr.execWidth = 8;
+ sel.MOV(GenRegister::retype(dst, GEN_TYPE_F), GenRegister::acc());
+ }
// Right part of the 16-wide register now
if (simdWidth == 16) {
&& reg.nr == GEN_ARF_NULL);
}
+ static INLINE GenRegister vec1(GenRegister reg) {
+ reg.width = GEN_WIDTH_1;
+ reg.hstride = GEN_HORIZONTAL_STRIDE_0;
+ reg.vstride = GEN_VERTICAL_STRIDE_0;
+ return reg;
+ }
+
static INLINE GenRegister acc(void) {
return GenRegister(GEN_ARCHITECTURE_REGISTER_FILE,
GEN_ARF_ACCUMULATOR,