Identified by Pedro Giffuni in PR27636.
llvm-svn: 287333
return false;
}
- // We cannot read LDS source registrs from the Trans slot.
+ // We cannot read LDS source registers from the Trans slot.
if (isTransSlot && TII->readsLDSSrcReg(MI))
return false;
def : ROTRPattern <V_ALIGNBIT_B32>;
/********** ====================== **********/
-/********** Indirect adressing **********/
+/********** Indirect addressing **********/
/********** ====================== **********/
multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> {
// If we need to perform a logical operation on i1 values, we need to
// use vector comparisons since there is only one SCC register. Vector
-// comparisions still write to a pair of SGPRs, so treat these as
+// comparisons still write to a pair of SGPRs, so treat these as
// 64-bit comparisons. When legalizing SGPR copies, instructions
// resulting in the copies from SCC to these instructions will be
// moved to the VALU.
// The block creation algorithm is divided into several steps, and several
// variants can be tried during the scheduling process.
//
-// Second the order of the instructions inside the blocks is choosen.
+// Second the order of the instructions inside the blocks is chosen.
// At that step we do take into account only register usage and hiding
// low latency instructions
//
-// Third the block order is choosen, there we try to hide high latencies
+// Third the block order is chosen, there we try to hide high latencies
// and keep register usage low.
//
// After the third step, a pass is done to improve the hiding of low
//
// Actually when talking about 'low latency' or 'high latency' it includes
// both the latency to get the cache (or global mem) data go to the register,
-// and the bandwith limitations.
+// and the bandwidth limitations.
// Increasing the number of active wavefronts helps hide the former, but it
// doesn't solve the latter, thus why even if wavefront count is high, we have
// to try have as many instructions hiding high latencies as possible.
// we haven't waited for
// . Low latencies
// . All other instructions
- // Goal is to get: low latency instructions - independant instructions
+ // Goal is to get: low latency instructions - independent instructions
// - (eventually some more low latency instructions)
// - instructions that depend on the first low latency instructions.
// If in the block there is a lot of constant loads, the SGPR usage
DAG->getBB()->splice(CurrentTopFastSched, DAG->getBB(), MI);
// Update LiveIntervals.
- // Note: Moving all instructions and calling handleMove everytime
+ // Note: Moving all instructions and calling handleMove every time
// is the most cpu intensive operation of the scheduler.
// It would gain a lot if there was a way to recompute the
// LiveIntervals for the entire scheduling region.
Requested = 0;
// If more SGPRs are required to support the input user/system SGPRs,
- // increase to accomodate them.
+ // increase to accommodate them.
//
// FIXME: This really ends up using the requested number of SGPRs + number
// of reserved special registers in total. Theoretically you could re-use
VOPAnyCommon <outs, ins, asm, pattern> {
// Using complex patterns gives VOP3 patterns a very high complexity rating,
- // but standalone patterns are almost always prefered, so we need to adjust the
+ // but standalone patterns are almost always preferred, so we need to adjust the
// priority lower. The goal is to use a high number to reduce complexity to
// zero (or less than zero).
let AddedComplexity = -1000;
let hasPostISelHook = 1;
// Using complex patterns gives VOP3 patterns a very high complexity rating,
- // but standalone patterns are almost always prefered, so we need to adjust the
+ // but standalone patterns are almost always preferred, so we need to adjust the
// priority lower. The goal is to use a high number to reduce complexity to
// zero (or less than zero).
let AddedComplexity = -1000;