drm/amd/display: Added Opp and Diags Interface for P to I

Signed-off-by: Arun Pandey <Arun.Pandey@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index ffce33fb55405eeb0acdddb71a67284595737190..0bc1cb88999242ec5eac7a1574eaae1832be3011 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -431,13 +431,13 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
                struct dc *dc)
 {
        struct dc_stream_state *stream = pipe_ctx->stream;
+       struct mpc *mpc = dc->res_pool->mpc;
        enum dc_color_space color_space;
        struct tg_color black_color = {0};
        bool enableStereo    = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
                        false:true;
        bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY;
 
-
        /* by upper caller loop, pipe0 is parent pipe and be called first.
         * back end is set up by for pipe0. Other children pipe share back end
         * with pipe 0. No program is needed.

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 5028619d4fb40b2920d37d2c20f4900f1b5cf66b..b016f4cbd45c74c5931ad9693d8cd3b5a3da69ce 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -335,7 +335,7 @@ void mpc10_update_blend_mode(
                        MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha);
 }
 
-static int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id)
+int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id)
 {
        struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
        int opp_id = 0xF;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
index 683ce4aaa76eff39d2df1b6c14f0b7e5bc19d3c6..e85e1f342266b7bcad3f7a11ae3c4fb91c2f24b7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
@@ -134,5 +134,6 @@ void mpc10_assert_idle_mpcc(
 void mpc10_update_blend_mode(
                struct mpc *mpc,
                struct mpcc_cfg *cfg);
+int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id);
 
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index 71385a004f52892458bead342d5905c599be561d..341210060cf7fc188fb2aa3b59fae0d2ace9e2d0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -38,25 +38,6 @@
        oppn10->base.ctx
 
 
-enum dpg_mode {
-       /* RGB colour block mode */
-       DPG_MODE_RGB_COLOUR_BLOCK,
-       /* YCbCr-601 colour block mode */
-       DPG_MODE_YCBCR_601_COLOUR_BLOCK,
-       /* YCbCr-709 colour block mode */
-       DPG_MODE_YCBCR_709_COLOUR_BLOCK,
-       /* Vertical bar mode */
-       DPG_MODE_VERTICAL_BAR,
-       /* Horizontal bar mode */
-       DPG_MODE_HORIZONTAL_BAR,
-       /* Single ramp mode */
-       DPG_MODE_RGB_SINGLE_RAMP,
-       /* Dual ramp mode */
-       DPG_MODE_RGB_DUAL_RAMP,
-       /* RGB XR BIAS mode */
-       DPG_MODE_RGB_XR_BIAS
-};
-
 /************* FORMATTER ************/
 
 /**
@@ -154,7 +135,7 @@ static void opp1_set_spatial_dither(
                        FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
 }
 
-static void opp1_program_bit_depth_reduction(
+void opp1_program_bit_depth_reduction(
        struct output_pixel_processor *opp,
        const struct bit_depth_reduction_params *params)
 {
@@ -242,7 +223,7 @@ static void opp1_set_clamping(
 
 }
 
-static void opp1_set_dyn_expansion(
+void opp1_set_dyn_expansion(
        struct output_pixel_processor *opp,
        enum dc_color_space color_sp,
        enum dc_color_depth color_dpth,
@@ -292,7 +273,7 @@ static void opp1_program_clamping_and_pixel_encoding(
        opp1_set_pixel_encoding(oppn10, params);
 }
 
-static void opp1_program_fmt(
+void opp1_program_fmt(
        struct output_pixel_processor *opp,
        struct bit_depth_reduction_params *fmt_bit_depth,
        struct clamping_and_pixel_encoding_params *clamping)
@@ -315,7 +296,7 @@ static void opp1_program_fmt(
        return;
 }
 
-static void opp1_set_stereo_polarity(
+void opp1_set_stereo_polarity(
                struct output_pixel_processor *opp,
                bool enable, bool rightEyePolarity)
 {
@@ -328,7 +309,7 @@ static void opp1_set_stereo_polarity(
 /* Constructor, Destructor               */
 /*****************************************/
 
-static void opp1_destroy(struct output_pixel_processor **opp)
+void opp1_destroy(struct output_pixel_processor **opp)
 {
        kfree(TO_DCN10_OPP(*opp));
        *opp = NULL;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
index cdb220ed858e6fcacf432d9f0d4ff0b83b18190a..4b1e51050d33eba815769178359b761bb88e7f0f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
@@ -74,18 +74,6 @@
        OPP_MASK_SH_LIST_DCN(mask_sh)
 
 #define OPP_DCN10_REG_FIELD_LIST(type) \
-       type DPG_EN; \
-       type DPG_MODE; \
-       type DPG_VRES; \
-       type DPG_HRES; \
-       type DPG_ACTIVE_WIDTH; \
-       type DPG_ACTIVE_HEIGHT; \
-       type DPG_COLOUR0_R_CR; \
-       type DPG_COLOUR1_R_CR; \
-       type DPG_COLOUR0_B_CB; \
-       type DPG_COLOUR1_B_CB; \
-       type DPG_COLOUR0_G_Y; \
-       type DPG_COLOUR1_G_Y; \
        type FMT_TRUNCATE_EN; \
        type FMT_TRUNCATE_DEPTH; \
        type FMT_TRUNCATE_MODE; \
@@ -118,11 +106,6 @@ struct dcn10_opp_mask {
 };
 
 struct dcn10_opp_registers {
-       uint32_t DPG_CONTROL;
-       uint32_t DPG_DIMENSIONS;
-       uint32_t DPG_COLOUR_B_CB;
-       uint32_t DPG_COLOUR_G_Y;
-       uint32_t DPG_COLOUR_R_CR;
        uint32_t FMT_BIT_DEPTH_CONTROL;
        uint32_t FMT_CONTROL;
        uint32_t FMT_DITHER_RAND_R_SEED;
@@ -150,4 +133,25 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10,
        const struct dcn10_opp_shift *opp_shift,
        const struct dcn10_opp_mask *opp_mask);
 
+void opp1_set_dyn_expansion(
+       struct output_pixel_processor *opp,
+       enum dc_color_space color_sp,
+       enum dc_color_depth color_dpth,
+       enum signal_type signal);
+
+void opp1_program_fmt(
+       struct output_pixel_processor *opp,
+       struct bit_depth_reduction_params *fmt_bit_depth,
+       struct clamping_and_pixel_encoding_params *clamping);
+
+void opp1_program_bit_depth_reduction(
+       struct output_pixel_processor *opp,
+       const struct bit_depth_reduction_params *params);
+
+void opp1_set_stereo_polarity(
+               struct output_pixel_processor *opp,
+               bool enable, bool rightEyePolarity);
+
+void opp1_destroy(struct output_pixel_processor **opp);
+
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index cd6b0d4cd457ab55bfff35246c9dd27af1d2a06a..579d1059a3d467aebf79215b789b915cd47d5ec8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -281,6 +281,21 @@ struct opp_funcs {
                        bool enable,
                        bool rightEyePolarity);
 
+       void (*opp_set_test_pattern)(
+                       struct output_pixel_processor *opp,
+                       bool enable);
+
+       void (*opp_dpg_blank_enable)(
+                       struct output_pixel_processor *opp,
+                       bool enable,
+                       const struct tg_color *color,
+                       int width,
+                       int height);
+
+       void (*opp_convert_pti)(
+               struct output_pixel_processor *opp,
+               bool enable,
+               bool polarity);
 };
 
 #endif