void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics);
+int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
+ bool enablement);
+
#endif
#endif
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.get_gpu_metrics = arcturus_get_gpu_metrics,
+ .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
};
void arcturus_set_ppt_funcs(struct smu_context *smu)
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.get_gpu_metrics = navi10_get_gpu_metrics,
.enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
+ .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
};
void navi10_set_ppt_funcs(struct smu_context *smu)
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
.enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
+ .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
};
void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
}
+
+int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
+ bool enablement)
+{
+ int ret = 0;
+
+ if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
+ ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
+
+ return ret;
+}