platform/x86: pmc_core: Use descriptive names for LPM registers
authorDavid E. Box <david.e.box@linux.intel.com>
Tue, 6 Oct 2020 22:47:00 +0000 (15:47 -0700)
committerHans de Goede <hdegoede@redhat.com>
Wed, 7 Oct 2020 21:05:53 +0000 (23:05 +0200)
TigerLake Lower Power Mode (LPM) registers are grouped by functionality
but were given simple enumerated names in the code (lpm0, lpm1, ...).
Instead, give the register blocks names that describe their usage.

Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20201006224702.12697-2-david.e.box@linux.intel.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
drivers/platform/x86/intel_pmc_core.c

index 338ea5222555a2300d38e8cdf4082fedcea6d3ff..ed9fdf7c8928cc692c5e2e3b835ffefeabab42a3 100644 (file)
@@ -409,7 +409,7 @@ static const struct pmc_reg_map icl_reg_map = {
        .ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
 };
 
-static const struct pmc_bit_map tgl_lpm0_map[] = {
+static const struct pmc_bit_map tgl_clocksource_status_map[] = {
        {"USB2PLL_OFF_STS",                     BIT(18)},
        {"PCIe/USB3.1_Gen2PLL_OFF_STS",         BIT(19)},
        {"PCIe_Gen3PLL_OFF_STS",                BIT(20)},
@@ -425,7 +425,7 @@ static const struct pmc_bit_map tgl_lpm0_map[] = {
        {}
 };
 
-static const struct pmc_bit_map tgl_lpm1_map[] = {
+static const struct pmc_bit_map tgl_power_gating_status_map[] = {
        {"SPI_PG_STS",                          BIT(2)},
        {"xHCI_PG_STS",                         BIT(3)},
        {"PCIe_Ctrller_A_PG_STS",               BIT(4)},
@@ -453,7 +453,7 @@ static const struct pmc_bit_map tgl_lpm1_map[] = {
        {}
 };
 
-static const struct pmc_bit_map tgl_lpm2_map[] = {
+static const struct pmc_bit_map tgl_d3_status_map[] = {
        {"ADSP_D3_STS",                         BIT(0)},
        {"SATA_D3_STS",                         BIT(1)},
        {"xHCI0_D3_STS",                        BIT(2)},
@@ -468,7 +468,7 @@ static const struct pmc_bit_map tgl_lpm2_map[] = {
        {}
 };
 
-static const struct pmc_bit_map tgl_lpm3_map[] = {
+static const struct pmc_bit_map tgl_vnn_req_status_map[] = {
        {"GPIO_COM0_VNN_REQ_STS",               BIT(1)},
        {"GPIO_COM1_VNN_REQ_STS",               BIT(2)},
        {"GPIO_COM2_VNN_REQ_STS",               BIT(3)},
@@ -493,7 +493,7 @@ static const struct pmc_bit_map tgl_lpm3_map[] = {
        {}
 };
 
-static const struct pmc_bit_map tgl_lpm4_map[] = {
+static const struct pmc_bit_map tgl_vnn_misc_status_map[] = {
        {"CPU_C10_REQ_STS_0",                   BIT(0)},
        {"PCIe_LPM_En_REQ_STS_3",               BIT(3)},
        {"ITH_REQ_STS_5",                       BIT(5)},
@@ -509,7 +509,7 @@ static const struct pmc_bit_map tgl_lpm4_map[] = {
        {}
 };
 
-static const struct pmc_bit_map tgl_lpm5_map[] = {
+static const struct pmc_bit_map tgl_signal_status_map[] = {
        {"LSX_Wake0_En_STS",                    BIT(0)},
        {"LSX_Wake0_Pol_STS",                   BIT(1)},
        {"LSX_Wake1_En_STS",                    BIT(2)},
@@ -546,12 +546,12 @@ static const struct pmc_bit_map tgl_lpm5_map[] = {
 };
 
 static const struct pmc_bit_map *tgl_lpm_maps[] = {
-       tgl_lpm0_map,
-       tgl_lpm1_map,
-       tgl_lpm2_map,
-       tgl_lpm3_map,
-       tgl_lpm4_map,
-       tgl_lpm5_map,
+       tgl_clocksource_status_map,
+       tgl_power_gating_status_map,
+       tgl_d3_status_map,
+       tgl_vnn_req_status_map,
+       tgl_vnn_misc_status_map,
+       tgl_signal_status_map,
        NULL
 };