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arm64: zynqmp: Enable FPGA loading from SPL
author
Michal Simek
<michal.simek@xilinx.com>
Mon, 5 Oct 2020 13:43:44 +0000
(15:43 +0200)
committer
Michal Simek
<michal.simek@xilinx.com>
Tue, 27 Oct 2020 07:13:31 +0000
(08:13 +0100)
fpga bitstream needs to be listed in config node in FIT image. Only tested
option is bitstream in BIN format.
Enabling this feature increase code size by almost 4k.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
configs/xilinx_zynqmp_virt_defconfig
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diff --git
a/configs/xilinx_zynqmp_virt_defconfig
b/configs/xilinx_zynqmp_virt_defconfig
index
264b662
..
5b4fe53
100644
(file)
--- a/
configs/xilinx_zynqmp_virt_defconfig
+++ b/
configs/xilinx_zynqmp_virt_defconfig
@@
-19,6
+19,7
@@
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_FPGA=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y