arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS

On the GENI SPI controller is is not very efficient if the chip select
line is controlled by the QUP itself (see 37dd4b777942 ("arm64: dts:
qcom: sc7180: Provide pinconf for SPI to use GPIO for CS") for the
details). Configure SPI0 CS pin as a GPIO.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210210133458.1201066-5-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index 973a615..5f41de2 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -949,7 +949,8 @@
 &spi0 {
        status = "okay";
        pinctrl-names = "default";
-       pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+       pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs_gpio>;
+       cs-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
 
        can@0 {
                compatible = "microchip,mcp2518fd";
@@ -1352,7 +1353,7 @@
 };
 
 /* PINCTRL - additions to nodes defined in sm8250.dtsi */
-&qup_spi0_cs {
+&qup_spi0_cs_gpio {
        drive-strength = <6>;
        bias-disable;
 };