unsigned MIFlags) const {
MachineFunction &MF = *MBB.getParent();
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
+ const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
DebugLoc DL;
- SmallVector<std::pair<unsigned,bool>, 4> Regs;
+ typedef std::pair<unsigned, bool> RegAndKill;
+ SmallVector<RegAndKill, 4> Regs;
unsigned i = CSI.size();
while (i != 0) {
unsigned LastReg = 0;
if (Regs.empty())
continue;
+
+ std::sort(Regs.begin(), Regs.end(), [&](RegAndKill &LHS, RegAndKill &RHS) {
+ return TRI.getEncodingValue(LHS.first) < TRI.getEncodingValue(RHS.first);
+ });
+
if (Regs.size() > 1 || StrOpc== 0) {
MachineInstrBuilder MIB =
AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
unsigned NumAlignedDPRCS2Regs) const {
MachineFunction &MF = *MBB.getParent();
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
+ const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
DebugLoc DL;
bool isTailCall = false;
if (Regs.empty())
continue;
+
+ std::sort(Regs.begin(), Regs.end(), [&](unsigned &LHS, unsigned &RHS) {
+ return TRI.getEncodingValue(LHS) < TRI.getEncodingValue(RHS);
+ });
+
if (Regs.size() > 1 || LdrOpc == 0) {
MachineInstrBuilder MIB =
AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
; CHECK-ARMV7-LABEL: _params_in_reg
; Store callee saved registers excluding swifterror.
-; CHECK-ARMV7: push {r8, r10, r11, r4, r5, r7, lr}
+; CHECK-ARMV7: push {r4, r5, r7, r8, r10, r11, lr}
; Store swiftself (r10) and swifterror (r6).
; CHECK-ARMV7-DAG: str r6, [s[[STK1:.*]]]
; CHECK-ARMV7-DAG: str r10, [s[[STK2:.*]]]
; CHECK-ARMV7: mov r2, r5
; CHECK-ARMV7: mov r3, r4
; CHECK-ARMV7: bl _params_in_reg2
-; CHECK-ARMV7: pop {r8, r10, r11, r4, r5, r7, pc}
+; CHECK-ARMV7: pop {r4, r5, r7, r8, r10, r11, pc}
define swiftcc void @params_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
%error_ptr_ref = alloca swifterror %swift_error*, align 8
store %swift_error* null, %swift_error** %error_ptr_ref
declare swiftcc void @params_in_reg2(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err)
; CHECK-ARMV7-LABEL: params_and_return_in_reg
-; CHECK-ARMV7: push {r8, r10, r11, r4, r5, r7, lr}
+; CHECK-ARMV7: push {r4, r5, r7, r8, r10, r11, lr}
; Store swifterror and swiftself
; CHECK-ARMV7: mov r4, r6
; CHECK-ARMV7: str r10, [s[[STK1:.*]]]
; CHECK-ARMV7: mov r1, r4
; CHECK-ARMV7: mov r2, r8
; CHECK-ARMV7: mov r3, r11
-; CHECK-ARMV7: pop {r8, r10, r11, r4, r5, r7, pc}
+; CHECK-ARMV7: pop {r4, r5, r7, r8, r10, r11, pc}
define swiftcc { i32, i32, i32, i32} @params_and_return_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
%error_ptr_ref = alloca swifterror %swift_error*, align 8
store %swift_error* null, %swift_error** %error_ptr_ref