let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[ICXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr",
- "(V?)CVTDQ2PSrr",
- "VCVTPD2QQ(Z128|Z256)rr",
+def: InstRW<[ICXWriteResGroup50], (instregex "VCVTPD2QQ(Z128|Z256)rr",
"VCVTPD2UQQ(Z128|Z256)rr",
"VCVTPS2DQ(Y|Z128|Z256)rr",
"(V?)CVTPS2DQrr",
"VCVTPS2UDQ(Z128|Z256)rr",
- "VCVTQQ2PD(Z128|Z256)rr",
"VCVTTPD2QQ(Z128|Z256)rr",
"VCVTTPD2UQQ(Z128|Z256)rr",
"VCVTTPS2DQ(Z128|Z256)rr",
"(V?)CVTTPS2DQrr",
- "VCVTTPS2UDQ(Z128|Z256)rr",
- "VCVTUDQ2PS(Z128|Z256)rr",
- "VCVTUQQ2PD(Z128|Z256)rr")>;
+ "VCVTTPS2UDQ(Z128|Z256)rr")>;
def ICXWriteResGroup50z : SchedWriteRes<[ICXPort05]> {
let Latency = 4;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[ICXWriteResGroup50z], (instrs VCVTDQ2PSZrr,
- VCVTPD2QQZrr,
+def: InstRW<[ICXWriteResGroup50z], (instrs VCVTPD2QQZrr,
VCVTPD2UQQZrr,
VCVTPS2DQZrr,
VCVTPS2UDQZrr,
- VCVTQQ2PDZrr,
VCVTTPD2QQZrr,
VCVTTPD2UQQZrr,
VCVTTPS2DQZrr,
- VCVTTPS2UDQZrr,
- VCVTUDQ2PSZrr,
- VCVTUQQ2PDZrr)>;
+ VCVTTPS2UDQZrr)>;
def ICXWriteResGroup51 : SchedWriteRes<[ICXPort5]> {
let Latency = 4;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr",
- "(V?)CVTDQ2PSrr",
- "VCVTPD2QQ(Z128|Z256)rr",
+def: InstRW<[SKXWriteResGroup50], (instregex "VCVTPD2QQ(Z128|Z256)rr",
"VCVTPD2UQQ(Z128|Z256)rr",
"VCVTPS2DQ(Y|Z128|Z256)rr",
"(V?)CVTPS2DQrr",
"VCVTPS2UDQ(Z128|Z256)rr",
- "VCVTQQ2PD(Z128|Z256)rr",
"VCVTTPD2QQ(Z128|Z256)rr",
"VCVTTPD2UQQ(Z128|Z256)rr",
"VCVTTPS2DQ(Z128|Z256)rr",
"(V?)CVTTPS2DQrr",
- "VCVTTPS2UDQ(Z128|Z256)rr",
- "VCVTUDQ2PS(Z128|Z256)rr",
- "VCVTUQQ2PD(Z128|Z256)rr")>;
+ "VCVTTPS2UDQ(Z128|Z256)rr")>;
def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> {
let Latency = 4;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr,
- VCVTPD2QQZrr,
+def: InstRW<[SKXWriteResGroup50z], (instrs VCVTPD2QQZrr,
VCVTPD2UQQZrr,
VCVTPS2DQZrr,
VCVTPS2UDQZrr,
- VCVTQQ2PDZrr,
VCVTTPD2QQZrr,
VCVTTPD2UQQZrr,
VCVTTPS2DQZrr,
- VCVTTPS2UDQZrr,
- VCVTUDQ2PSZrr,
- VCVTUQQ2PDZrr)>;
+ VCVTTPS2UDQZrr)>;
def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
let Latency = 4;