PCI: dwc: Add dw_pcie_link_set_max_link_width()

[ Upstream commit a9a1bcba90254975d4adbcca53f720318cf81c0c ]

This is a preparation before adding the Max-Link-width capability
setup which would in its turn complete the max-link-width setup
procedure defined by Synopsys in the HW-manual.

Seeing there is a max-link-speed setup method defined in the DW PCIe
core driver it would be good to have a similar function for the link
width setup.

That's why we need to define a dedicated function first from already
implemented but incomplete link-width setting up code.

Link: https://lore.kernel.org/linux-pci/20231018085631.1121289-3-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 1c1c734..da4aba4 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -732,6 +732,46 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
 
 }
 
+static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
+{
+       u32 lwsc, plc;
+
+       if (!num_lanes)
+               return;
+
+       /* Set the number of lanes */
+       plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
+       plc &= ~PORT_LINK_FAST_LINK_MODE;
+       plc &= ~PORT_LINK_MODE_MASK;
+
+       /* Set link width speed control register */
+       lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+       lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK;
+       switch (num_lanes) {
+       case 1:
+               plc |= PORT_LINK_MODE_1_LANES;
+               lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES;
+               break;
+       case 2:
+               plc |= PORT_LINK_MODE_2_LANES;
+               lwsc |= PORT_LOGIC_LINK_WIDTH_2_LANES;
+               break;
+       case 4:
+               plc |= PORT_LINK_MODE_4_LANES;
+               lwsc |= PORT_LOGIC_LINK_WIDTH_4_LANES;
+               break;
+       case 8:
+               plc |= PORT_LINK_MODE_8_LANES;
+               lwsc |= PORT_LOGIC_LINK_WIDTH_8_LANES;
+               break;
+       default:
+               dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
+               return;
+       }
+       dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
+       dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
+}
+
 void dw_pcie_iatu_detect(struct dw_pcie *pci)
 {
        int max_region, ob, ib;
@@ -1013,49 +1053,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
        val |= PORT_LINK_DLL_LINK_EN;
        dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
 
-       if (!pci->num_lanes) {
-               dev_dbg(pci->dev, "Using h/w default number of lanes\n");
-               return;
-       }
-
-       /* Set the number of lanes */
-       val &= ~PORT_LINK_FAST_LINK_MODE;
-       val &= ~PORT_LINK_MODE_MASK;
-       switch (pci->num_lanes) {
-       case 1:
-               val |= PORT_LINK_MODE_1_LANES;
-               break;
-       case 2:
-               val |= PORT_LINK_MODE_2_LANES;
-               break;
-       case 4:
-               val |= PORT_LINK_MODE_4_LANES;
-               break;
-       case 8:
-               val |= PORT_LINK_MODE_8_LANES;
-               break;
-       default:
-               dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes);
-               return;
-       }
-       dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
-
-       /* Set link width speed control register */
-       val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
-       val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
-       switch (pci->num_lanes) {
-       case 1:
-               val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
-               break;
-       case 2:
-               val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
-               break;
-       case 4:
-               val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
-               break;
-       case 8:
-               val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
-               break;
-       }
-       dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+       dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
 }