snd_soc_get_enum_double, snd_soc_put_enum_double),
};
-static inline int get_clk_div(struct fsl_micfil *micfil,
- unsigned int rate)
-{
- long mclk_rate;
- int clk_div;
-
- mclk_rate = clk_get_rate(micfil->mclk);
-
- clk_div = mclk_rate / (rate * MICFIL_OSR_DEFAULT * 8);
-
- return clk_div;
-}
-
/* The SRES is a self-negated bit which provides the CPU with the
* capability to initialize the PDM Interface module through the
* slave-bus interface. This bit always reads as zero, and this
return 0;
}
-static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil,
- unsigned int freq)
-{
- struct device *dev = &micfil->pdev->dev;
- int ret;
-
- clk_disable_unprepare(micfil->mclk);
-
- ret = clk_set_rate(micfil->mclk, freq * 1024);
- if (ret)
- dev_warn(dev, "failed to set rate (%u): %d\n",
- freq * 1024, ret);
-
- clk_prepare_enable(micfil->mclk);
-
- return ret;
-}
-
static int fsl_micfil_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
static int fsl_set_clock_params(struct device *dev, unsigned int rate)
{
struct fsl_micfil *micfil = dev_get_drvdata(dev);
- int clk_div;
+ int clk_div = 8;
int ret;
- ret = fsl_micfil_set_mclk_rate(micfil, rate);
- if (ret < 0)
- dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
- clk_get_rate(micfil->mclk), rate);
+ ret = clk_set_rate(micfil->mclk, rate * clk_div * MICFIL_OSR_DEFAULT * 8);
+ if (ret)
+ return ret;
/* set CICOSR */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
if (ret)
return ret;
- /* set CLK_DIV */
- clk_div = get_clk_div(micfil, rate);
- if (clk_div < 0)
- ret = -EINVAL;
-
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_CLKDIV,
FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div));