arm: dts: sunxi: update H3 to new EMAC binding
authorAndre Przywara <andre.przywara@arm.com>
Wed, 4 Apr 2018 00:31:18 +0000 (01:31 +0100)
committerJagan Teki <jagan@amarulasolutions.com>
Wed, 4 Apr 2018 06:01:35 +0000 (11:31 +0530)
The U-Boot driver for the sun8i-emac was using some preliminary DT
binding. Now since Linux got its own driver in v4.15 and our driver
can now cope with both bindings, let's convert the DT nodes used by the
various H3 boards over to the new bindings used by the kernel.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts
arch/arm/dts/sun8i-h3-nanopi-neo.dts
arch/arm/dts/sun8i-h3-orangepi-2.dts
arch/arm/dts/sun8i-h3-orangepi-one.dts
arch/arm/dts/sun8i-h3-orangepi-pc.dts
arch/arm/dts/sun8i-h3-orangepi-plus.dts
arch/arm/dts/sun8i-h3-orangepi-plus2e.dts
arch/arm/dts/sun8i-h3.dtsi

index 20d489c..e0efcb3 100644 (file)
 };
 
 &emac {
-       phy = <&phy1>;
+       phy-handle = <&int_mii_phy>;
        phy-mode = "mii";
-       allwinner,use-internal-phy;
        allwinner,leds-active-low;
        status = "okay";
-       phy1: ethernet-phy@1 {
-               reg = <1>;
-       };
 };
 
 &mmc0 {
index 97b993f..c8fd69f 100644 (file)
 };
 
 &emac {
-       phy = <&phy1>;
+       phy-handle = <&int_mii_phy>;
        phy-mode = "mii";
-       allwinner,use-internal-phy;
        allwinner,leds-active-low;
        status = "okay";
-
-       phy1: ethernet-phy@1 {
-               reg = <1>;
-       };
 };
 
 &ir {
index 5113059..78f6c24 100644 (file)
 };
 
 &emac {
-       phy = <&phy1>;
+       phy-handle = <&int_mii_phy>;
        phy-mode = "mii";
-       allwinner,use-internal-phy;
        allwinner,leds-active-low;
        status = "okay";
-       phy1: ethernet-phy@1 {
-               reg = <1>;
-       };
 };
index caa1a69..d97fdac 100644 (file)
@@ -55,6 +55,7 @@
        aliases {
                serial0 = &uart0;
                /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+               ethernet0 = &emac;
                ethernet1 = &rtl8189;
        };
 
 };
 
 &emac {
-       phy = <&phy1>;
+       phy-handle = <&int_mii_phy>;
        phy-mode = "mii";
-       allwinner,use-internal-phy;
        allwinner,leds-active-low;
        status = "okay";
-       phy1: ethernet-phy@1 {
-               reg = <1>;
-       };
 };
 
 &ir {
index 8df5c74..adab1cb 100644 (file)
@@ -53,6 +53,7 @@
        compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
 
        aliases {
+               ethernet0 = &emac;
                serial0 = &uart0;
        };
 
 };
 
 &emac {
-       phy = <&phy1>;
+       phy-handle = <&int_mii_phy>;
        phy-mode = "mii";
-       allwinner,use-internal-phy;
        allwinner,leds-active-low;
        status = "okay";
-       phy1: ethernet-phy@1 {
-               reg = <1>;
-       };
 };
 
 &mmc0 {
index b8340f7..afba264 100644 (file)
@@ -53,6 +53,7 @@
        compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
 
        aliases {
+               ethernet0 = &emac;
                serial0 = &uart0;
        };
 
 };
 
 &emac {
-       phy = <&phy1>;
+       phy-handle = <&int_mii_phy>;
        phy-mode = "mii";
-       allwinner,use-internal-phy;
        allwinner,leds-active-low;
        status = "okay";
-       phy1: ethernet-phy@1 {
-               reg = <1>;
-       };
 };
index e7079b2..136e441 100644 (file)
        pinctrl-0 = <&emac_rgmii_pins>;
        phy-supply = <&reg_gmac_3v3>;
        phy-mode = "rgmii";
-       /delete-property/allwinner,use-internal-phy;
+};
+
+&external_mdio {
+       ext_rgmii_phy: ethernet-phy@1 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <0>;
+       };
 };
 
 &mmc2 {
index f97b040..51aaf49 100644 (file)
        pinctrl-names = "default";
        pinctrl-0 = <&emac_rgmii_pins>;
        phy-supply = <&reg_gmac_3v3>;
+       phy-handle = <&ext_rgmii_phy>;
        phy-mode = "rgmii";
-       /delete-property/allwinner,use-internal-phy;
+};
+
+&external_mdio {
+       ext_rgmii_phy: ethernet-phy@1 {
+               compatible = "ethernet-phy-ieee802.3-c22";
+               reg = <1>;
+       };
 };
 
 &pio {
index afa6079..d9d31fa 100644 (file)
                #size-cells = <1>;
                ranges;
 
-               syscon: syscon@01c00000 {
-                       compatible = "allwinner,sun8i-h3-syscon","syscon";
-                       reg = <0x01c00000 0x34>;
+               syscon: syscon@1c00000 {
+                       compatible = "allwinner,sun8i-h3-system-controller",
+                                    "syscon";
+                       reg = <0x01c00000 0x1000>;
                };
 
                dma: dma-controller@01c02000 {
                        interrupt-controller;
                        #interrupt-cells = <3>;
 
-                       emac_rgmii_pins: emac0@0 {
-                               allwinner,pins = "PD0", "PD1", "PD2", "PD3",
-                                               "PD4", "PD5", "PD7",
-                                               "PD8", "PD9", "PD10",
-                                               "PD12", "PD13", "PD15",
-                                               "PD16", "PD17";
-                               allwinner,function = "emac";
-                               allwinner,drive = <SUN4I_PINCTRL_40_MA>;
-                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                       emac_rgmii_pins: emac0 {
+                               pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+                                      "PD5", "PD7", "PD8", "PD9", "PD10",
+                                      "PD12", "PD13", "PD15", "PD16", "PD17";
+                               function = "emac";
+                               drive-strength = <40>;
                        };
 
                        mmc0_pins_a: mmc0@0 {
 
                emac: ethernet@1c30000 {
                        compatible = "allwinner,sun8i-h3-emac";
-                       reg = <0x01c30000 0x104>, <0x01c00030 0x4>;
-                       reg-names = "emac", "syscon";
+                       syscon = <&syscon>;
+                       reg = <0x01c30000 0x10000>;
                        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-                       resets = <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>;
-                       reset-names = "ahb", "ephy";
-                       clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>;
-                       clock-names = "ahb", "ephy";
+                       interrupt-names = "macirq";
+                       resets = <&ccu RST_BUS_EMAC>;
+                       reset-names = "stmmaceth";
+                       clocks = <&ccu CLK_BUS_EMAC>;
+                       clock-names = "stmmaceth";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        status = "disabled";
+
+                       mdio: mdio {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "snps,dwmac-mdio";
+                       };
+
+                       mdio-mux {
+                               compatible = "allwinner,sun8i-h3-mdio-mux";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               mdio-parent-bus = <&mdio>;
+                               /* Only one MDIO is usable at the time */
+                               internal_mdio: mdio@1 {
+                                       compatible = "allwinner,sun8i-h3-mdio-internal";
+                                       reg = <1>;
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       int_mii_phy: ethernet-phy@1 {
+                                               compatible = "ethernet-phy-ieee802.3-c22";
+                                               reg = <1>;
+                                               clocks = <&ccu CLK_BUS_EPHY>;
+                                               resets = <&ccu RST_BUS_EPHY>;
+                                       };
+                               };
+
+                               external_mdio: mdio@2 {
+                                       reg = <2>;
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                               };
+                       };
                };
 
                gic: interrupt-controller@01c81000 {