drm/radeon: disable the crtcs in mc_stop (r5xx-r7xx) (v2)
authorAlex Deucher <alexander.deucher@amd.com>
Wed, 17 Apr 2013 13:35:39 +0000 (09:35 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 22 Apr 2013 14:39:09 +0000 (10:39 -0400)
Just disabling the mem requests should be enough, but
that doesn't seem to work correctly on efi systems.

v2: blank displays first, then disable.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drivers/gpu/drm/radeon/r500_reg.h
drivers/gpu/drm/radeon/rv515.c

index b524209..1dd0d32 100644 (file)
 
 #define AVIVO_D1MODE_MASTER_UPDATE_LOCK                         0x60e0
 #define AVIVO_D1MODE_MASTER_UPDATE_MODE                         0x60e4
+#define AVIVO_D1CRTC_UPDATE_LOCK                                0x60e8
 
 /* master controls */
 #define AVIVO_DC_CRTC_MASTER_EN                                 0x60f8
index 6a1e5dd..ffcba73 100644 (file)
@@ -303,8 +303,10 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
                        tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
                        if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
                                radeon_wait_for_vblank(rdev, i);
+                               WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
                                tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
                                WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
+                               WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
                        }
                        /* wait for the next frame */
                        frame_count = radeon_get_vblank_counter(rdev, i);
@@ -313,6 +315,15 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
                                        break;
                                udelay(1);
                        }
+
+                       /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
+                       WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+                       tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
+                       tmp &= ~AVIVO_CRTC_EN;
+                       WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
+                       WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+                       save->crtc_enabled[i] = false;
+                       /* ***** */
                } else {
                        save->crtc_enabled[i] = false;
                }