lib: sbi: fwft: check feature value to be exactly 1 or 0
authorClément Léger <cleger@rivosinc.com>
Mon, 24 Jun 2024 10:29:08 +0000 (12:29 +0200)
committerAnup Patel <anup@brainfault.org>
Wed, 26 Jun 2024 12:43:54 +0000 (18:13 +0530)
As stated by the spec and pointed out by Andrew Jones, the value passed
for MISALIGNED_EXC_DELEG and PTE_AD_HW_UPDATING should be either 0 or 1.
Add check for these values and return SBI_EINVAL if not.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
lib/sbi/sbi_fwft.c

index aff087fbc62945cab5161cb4aff20581f4894745..595819b6877fbd4455475bcb89d13cfa3cf15de6 100644 (file)
@@ -84,10 +84,12 @@ static int fwft_misaligned_delegation_supported(struct fwft_config *conf)
 static int fwft_set_misaligned_delegation(struct fwft_config *conf,
                                         unsigned long value)
 {
-       if (value)
+       if (value == 1)
                csr_set(CSR_MEDELEG, MIS_DELEG);
-       else
+       else if (value == 0)
                csr_clear(CSR_MEDELEG, MIS_DELEG);
+       else
+               return SBI_EINVAL;
 
        return SBI_OK;
 }
@@ -111,18 +113,20 @@ static int fwft_adue_supported(struct fwft_config *conf)
 
 static int fwft_set_adue(struct fwft_config *conf, unsigned long value)
 {
-       if (value)
+       if (value == 1)
 #if __riscv_xlen == 32
                csr_set(CSR_MENVCFGH, ENVCFG_ADUE >> 32);
 #else
                csr_set(CSR_MENVCFG, ENVCFG_ADUE);
 #endif
-       else
+       else if (value == 0)
 #if __riscv_xlen == 32
                csr_clear(CSR_MENVCFGH, ENVCFG_ADUE >> 32);
 #else
                csr_clear(CSR_MENVCFG, ENVCFG_ADUE);
 #endif
+       else
+               return SBI_EINVAL;
 
        return SBI_OK;
 }