#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x43 0x0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>;
+ interconnect-names = "qup-core";
status = "disabled";
i2c0: i2c@880000 {
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x4c3 0x0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>;
+ interconnect-names = "qup-core";
status = "disabled";
i2c6: i2c@a80000 {
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart6_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart7_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart8_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart9_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart10_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
pinctrl-names = "default";
pinctrl-0 = <&qup_uart11_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<&gcc GCC_QSPI_CORE_CLK>;
clock-names = "iface", "core";
+ interconnects = <&gem_noc MASTER_APPSS_PROC
+ &config_noc SLAVE_QSPI_0>;
+ interconnect-names = "qspi-config";
status = "disabled";
};