vlock: finetune vlock setting for game mode [1/1]

PD#TV-6913

Problem:
game mode, hdmi delay time too long

Solution:
fine tune setting, make tune P mode will got
the real phase.

Verify:
tl1 android P

Change-Id: I4c4a1d6d6578c5015b556f5e4cc88a592be4d7fa
Signed-off-by: Yong Qin <yong.qin@amlogic.com>

diff --git a/drivers/amlogic/media/enhancement/amvecm/vlock.c b/drivers/amlogic/media/enhancement/amvecm/vlock.c
index 1833382..6556a75 100644 (file)
--- a/drivers/amlogic/media/enhancement/amvecm/vlock.c
+++ b/drivers/amlogic/media/enhancement/amvecm/vlock.c
@@ -483,6 +483,10 @@ static void vlock_setting(struct vframe_s *vf,
                        else
                                WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
                                                1, 28, 1);
+               } else {
+                       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1))
+                               WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
+                                               1, 28, 1);
                }
                freq_hz = input_hz | (output_hz << 8);
                WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, freq_hz, 0, 16);
@@ -537,7 +541,7 @@ static void vlock_setting(struct vframe_s *vf,
                } else {
                        if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1))
                                WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
-                                               0, 28, 1);
+                                               1, 28, 1);
                }
                freq_hz = input_hz | (output_hz << 8);
                WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, freq_hz, 0, 16);
@@ -1768,11 +1772,13 @@ void vlock_phaselock_check(struct stvlock_sig_sts *pvlock,
 {
        /*vs_i*/
        u32 ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
+       u32 oa = READ_VPP_REG(VPU_VLOCK_RO_VS_O_DIST);
        u32 val, pre;
 
        if (vlock.phlock_en) {
-               if ((pvlock->frame_cnt_in%100) == 0) {
-                       ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
+               if ((pvlock->frame_cnt_in % 20) == 0) {
+                       /*ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);*/
+                       ia = (ia + oa) / 2;
                        pre = READ_VPP_REG(VPU_VLOCK_LOOP1_PHSDIF_TGT);
                        val = (ia * (100 + vlock.phlock_percent))/200;
                        if (val != pre) {

diff --git a/drivers/amlogic/media/enhancement/amvecm/vlock.h b/drivers/amlogic/media/enhancement/amvecm/vlock.h
index 97c30a5..673daad 100644 (file)
--- a/drivers/amlogic/media/enhancement/amvecm/vlock.h
+++ b/drivers/amlogic/media/enhancement/amvecm/vlock.h
@@ -23,7 +23,7 @@
 #include <linux/amlogic/media/vfm/vframe.h>
 #include "linux/amlogic/media/amvecm/ve.h"
 
-#define VLOCK_VER "Ref.2019/5/23:vlock for hdmi pll"
+#define VLOCK_VER "Ref.2019/6/18:finetune vlock setting"
 
 #define VLOCK_REG_NUM  33