radv: stop checking if patch control points is dynamic everywhere

Check that the values are non-zero instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24346>

diff --git a/src/amd/vulkan/nir/radv_nir_lower_abi.c b/src/amd/vulkan/nir/radv_nir_lower_abi.c
index b7c5b72..6489a82 100644 (file)
--- a/src/amd/vulkan/nir/radv_nir_lower_abi.c
+++ b/src/amd/vulkan/nir/radv_nir_lower_abi.c
@@ -97,14 +97,14 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
       replacement = ac_nir_load_arg(b, &s->args->ac, s->args->ac.tess_offchip_offset);
       break;
    case nir_intrinsic_load_tcs_num_patches_amd:
-      if (s->pl_key->dynamic_patch_control_points) {
+      if (s->info->num_tess_patches) {
+         replacement = nir_imm_int(b, s->info->num_tess_patches);
+      } else {
          if (stage == MESA_SHADER_TESS_CTRL) {
             replacement = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_NUM_PATCHES);
          } else {
             replacement = GET_SGPR_FIELD_NIR(s->args->tes_state, TES_STATE_NUM_PATCHES);
          }
-      } else {
-         replacement = nir_imm_int(b, s->info->num_tess_patches);
       }
       break;
    case nir_intrinsic_load_ring_esgs_amd:
@@ -158,10 +158,10 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
       break;
    case nir_intrinsic_load_patch_vertices_in:
       if (stage == MESA_SHADER_TESS_CTRL) {
-         if (s->pl_key->dynamic_patch_control_points) {
-            replacement = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS);
-         } else {
+         if (s->pl_key->tcs.tess_input_vertices) {
             replacement = nir_imm_int(b, s->pl_key->tcs.tess_input_vertices);
+         } else {
+            replacement = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS);
          }
       } else if (stage == MESA_SHADER_TESS_EVAL) {
          replacement = nir_imm_int(b, b->shader->info.tess.tcs_vertices_out);
@@ -283,7 +283,10 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
          stage == MESA_SHADER_TESS_CTRL ? s->info->tcs.num_linked_outputs : s->info->tes.num_linked_inputs;
       int per_vertex_output_patch_size = out_vertices_per_patch * num_tcs_outputs * 16u;
 
-      if (s->pl_key->dynamic_patch_control_points) {
+      if (s->info->num_tess_patches) {
+         unsigned num_patches = s->info->num_tess_patches;
+         replacement = nir_imm_int(b, num_patches * per_vertex_output_patch_size);
+      } else {
          nir_ssa_def *num_patches;
 
          if (stage == MESA_SHADER_TESS_CTRL) {
@@ -292,9 +295,6 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
             num_patches = GET_SGPR_FIELD_NIR(s->args->tes_state, TES_STATE_NUM_PATCHES);
          }
          replacement = nir_imul_imm(b, num_patches, per_vertex_output_patch_size);
-      } else {
-         unsigned num_patches = s->info->num_tess_patches;
-         replacement = nir_imm_int(b, num_patches * per_vertex_output_patch_size);
       }
       break;
    }

diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c
index d9e7af5..85524d1 100644 (file)
--- a/src/amd/vulkan/radv_shader_args.c
+++ b/src/amd/vulkan/radv_shader_args.c
@@ -353,6 +353,20 @@ radv_declare_rt_shader_args(enum amd_gfx_level gfx_level, struct radv_shader_arg
 }
 
 static bool
+radv_tcs_needs_state_sgpr(const struct radv_shader_info *info, const struct radv_pipeline_key *key)
+{
+   /* When the number of patch control points/tessellation patches is 0, it's loaded from a SGPR. */
+   return !key->tcs.tess_input_vertices || !info->num_tess_patches;
+}
+
+static bool
+radv_tes_needs_state_sgpr(const struct radv_shader_info *info)
+{
+   /* When the number of tessellation patches is 0, it's loaded from a SGPR. */
+   return !info->num_tess_patches;
+}
+
+static bool
 radv_ps_needs_state_sgpr(const struct radv_shader_info *info, const struct radv_pipeline_key *key)
 {
    if (info->ps.needs_sample_positions && key->dynamic_rasterization_samples)
@@ -512,7 +526,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
             add_ud_arg(args, 1, AC_ARG_INT, &args->ac.view_index, AC_UD_VIEW_INDEX);
          }
 
-         if (key->dynamic_patch_control_points) {
+         if (radv_tcs_needs_state_sgpr(info, key)) {
             add_ud_arg(args, 1, AC_ARG_INT, &args->tcs_offchip_layout, AC_UD_TCS_OFFCHIP_LAYOUT);
          }
 
@@ -527,7 +541,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
             add_ud_arg(args, 1, AC_ARG_INT, &args->ac.view_index, AC_UD_VIEW_INDEX);
          }
 
-         if (key->dynamic_patch_control_points) {
+         if (radv_tcs_needs_state_sgpr(info, key)) {
             add_ud_arg(args, 1, AC_ARG_INT, &args->tcs_offchip_layout, AC_UD_TCS_OFFCHIP_LAYOUT);
          }
 
@@ -549,7 +563,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
       if (needs_view_index)
          add_ud_arg(args, 1, AC_ARG_INT, &args->ac.view_index, AC_UD_VIEW_INDEX);
 
-      if (key->dynamic_patch_control_points)
+      if (radv_tes_needs_state_sgpr(info))
          add_ud_arg(args, 1, AC_ARG_INT, &args->tes_state, AC_UD_TES_STATE);
 
       if (info->tes.as_es) {
@@ -598,7 +612,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline
             add_ud_arg(args, 1, AC_ARG_INT, &args->ac.view_index, AC_UD_VIEW_INDEX);
          }
 
-         if (previous_stage == MESA_SHADER_TESS_EVAL && key->dynamic_patch_control_points)
+         if (previous_stage == MESA_SHADER_TESS_EVAL && radv_tes_needs_state_sgpr(info))
             add_ud_arg(args, 1, AC_ARG_INT, &args->tes_state, AC_UD_TES_STATE);
 
          if (previous_stage == MESA_SHADER_VERTEX && info->vs.dynamic_num_verts_per_prim)