ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR.
authorPeter Collingbourne <peter@pcc.me.uk>
Tue, 27 Feb 2018 19:00:59 +0000 (19:00 +0000)
committerPeter Collingbourne <peter@pcc.me.uk>
Tue, 27 Feb 2018 19:00:59 +0000 (19:00 +0000)
Differential Revision: https://reviews.llvm.org/D43807

llvm-svn: 326226

llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/test/CodeGen/Thumb2/cmp-frame.ll [new file with mode: 0644]

index e8259f7..179f113 100644 (file)
@@ -489,7 +489,8 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
     Offset += MI.getOperand(FrameRegIdx+1).getImm();
 
     unsigned PredReg;
-    if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL) {
+    if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL &&
+        !MI.definesRegister(ARM::CPSR)) {
       // Turn it into a move.
       MI.setDesc(TII.get(ARM::tMOVr));
       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
diff --git a/llvm/test/CodeGen/Thumb2/cmp-frame.ll b/llvm/test/CodeGen/Thumb2/cmp-frame.ll
new file mode 100644 (file)
index 0000000..ceb9697
--- /dev/null
@@ -0,0 +1,11 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "thumbv7-linux-androideabi"
+
+define i1 @f() {
+  %a = alloca i8*
+  ; CHECK: adds.w r0, sp, #0
+  ; CHECK: it ne
+  %cmp = icmp ne i8** %a, null
+  ret i1 %cmp
+}