Merge branch 'mpc86xx'

diff --combined include/asm-ppc/processor.h
index 14b9282,0060cd0..6e1d610
--- 1/include/asm-ppc/processor.h
--- 2/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@@ -264,7 -264,7 +264,7 @@@
  #define SPRN_ICTC     0x3FB   /* Instruction Cache Throttling Control Reg */
  #define SPRN_IMISS    0x3D4   /* Instruction TLB Miss Register */
  #define SPRN_IMMR     0x27E   /* Internal Memory Map Register */
- #define SPRN_LDSTCR     0x3F8   /* Load/Store Control Register */
+ #define SPRN_LDSTCR   0x3F8   /* Load/Store Control Register */
  #define SPRN_L2CR     0x3F9   /* Level 2 Cache Control Regsiter */
  #define SPRN_LR               0x008   /* Link Register */
  #define SPRN_MBAR       0x137   /* System memory base address */
@@@ -445,7 -445,7 +445,7 @@@
  #define ESR_ST          0x00800000      /* Store Operation */
  
  #if defined(CONFIG_MPC86xx)
- #define SPRN_MSSCRO     0x3f6
+ #define SPRN_MSSCRO   0x3f6
  #endif
  
  
@@@ -507,12 -507,12 +507,12 @@@
  #define ICMP  SPRN_ICMP       /* Instruction TLB Compare Register */
  #define IMISS SPRN_IMISS      /* Instruction TLB Miss Register */
  #define IMMR  SPRN_IMMR       /* PPC 860/821 Internal Memory Map Register */
- #define LDSTCR  SPRN_LDSTCR     /* Load/Store Control Register */
+ #define LDSTCR        SPRN_LDSTCR     /* Load/Store Control Register */
  #define L2CR  SPRN_L2CR       /* PPC 750 L2 control register */
  #define LR    SPRN_LR
  #define MBAR    SPRN_MBAR       /* System memory base address */
  #if defined(CONFIG_MPC86xx)
- #define MSSCR0  SPRN_MSSCRO
+ #define MSSCR0        SPRN_MSSCRO
  #endif
  #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
  #define PIR   SPRN_PIR
@@@ -548,7 -548,7 +548,7 @@@
  #define CSRR0 SPRN_CSRR0
  #define CSRR1 SPRN_CSRR1
  #define IVPR  SPRN_IVPR
- #define USPRG0 SPRN_USPRG
+ #define USPRG0        SPRN_USPRG
  #define SPRG4R        SPRN_SPRG4R
  #define SPRG5R        SPRN_SPRG5R
  #define SPRG6R        SPRN_SPRG6R
@@@ -735,9 -735,7 +735,9 @@@
  #define PVR_440GP_RC  0x40120481
  #define PVR_440EP_RA  0x42221850
  #define PVR_440EP_RB  0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
 +#define PVR_440EP_RC  0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
  #define PVR_440GR_RA  0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
 +#define PVR_440GR_RB  0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
  #define PVR_440GX_RA  0x51B21850
  #define PVR_440GX_RB  0x51B21851
  #define PVR_440GX_RC  0x51B21892
@@@ -745,8 -743,6 +745,8 @@@
  #define PVR_405EP_RB  0x51210950
  #define PVR_440SP_RA  0x53221850
  #define PVR_440SP_RB  0x53221891
 +#define PVR_440SPe_RA 0x53421890
 +#define PVR_440SPe_RB 0x53421891
  #define PVR_601               0x00010000
  #define PVR_602               0x00050000
  #define PVR_603               0x00030000