s32 ret_val;
if (hw->phy.media_type != e1000_media_type_copper) {
- phy->type = e1000_phy_none;
+ phy->type = e1000_phy_none;
return 0;
} else {
phy->ops.power_up = e1000_power_up_phy_copper;
phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
}
- phy->addr = 1;
- phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
- phy->reset_delay_us = 100;
- phy->type = e1000_phy_gg82563;
+ phy->addr = 1;
+ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+ phy->reset_delay_us = 100;
+ phy->type = e1000_phy_gg82563;
/* This can only be done after all function pointers are setup. */
ret_val = e1000e_get_phy_id(hw);
u32 eecd = er32(EECD);
u16 size;
- nvm->opcode_bits = 8;
- nvm->delay_usec = 1;
+ nvm->opcode_bits = 8;
+ nvm->delay_usec = 1;
switch (nvm->override) {
case e1000_nvm_override_spi_large:
- nvm->page_size = 32;
+ nvm->page_size = 32;
nvm->address_bits = 16;
break;
case e1000_nvm_override_spi_small:
- nvm->page_size = 8;
+ nvm->page_size = 8;
nvm->address_bits = 8;
break;
default:
- nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
+ nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
break;
}
/* EEPROM access above 16k is unsupported */
if (size > 14)
size = 14;
- nvm->word_size = 1 << size;
+ nvm->word_size = 1 << size;
return 0;
}
/* Transmit Arbitration Control 0 */
reg = er32(TARC(0));
- reg &= ~(0xF << 27); /* 30:27 */
+ reg &= ~(0xF << 27); /* 30:27 */
if (hw->phy.media_type != e1000_media_type_copper)
reg &= ~(1 << 20);
ew32(TARC(0), reg);
return 0;
}
- phy->addr = 1;
- phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
- phy->reset_delay_us = 100;
+ phy->addr = 1;
+ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+ phy->reset_delay_us = 100;
- phy->ops.power_up = e1000_power_up_phy_copper;
- phy->ops.power_down = e1000_power_down_phy_copper_82571;
+ phy->ops.power_up = e1000_power_up_phy_copper;
+ phy->ops.power_down = e1000_power_down_phy_copper_82571;
switch (hw->mac.type) {
case e1000_82571:
case e1000_82572:
- phy->type = e1000_phy_igp_2;
+ phy->type = e1000_phy_igp_2;
break;
case e1000_82573:
- phy->type = e1000_phy_m88;
+ phy->type = e1000_phy_m88;
break;
case e1000_82574:
case e1000_82583:
- phy->type = e1000_phy_bm;
+ phy->type = e1000_phy_bm;
phy->ops.acquire = e1000_get_hw_semaphore_82574;
phy->ops.release = e1000_put_hw_semaphore_82574;
phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
/* EEPROM access above 16k is unsupported */
if (size > 14)
size = 14;
- nvm->word_size = 1 << size;
+ nvm->word_size = 1 << size;
break;
}
static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
{
struct e1000_hw *hw = &adapter->hw;
- static int global_quad_port_a; /* global port a indication */
+ static int global_quad_port_a; /* global port a indication */
struct pci_dev *pdev = adapter->pdev;
int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
s32 rc;
/* Transmit Arbitration Control 0 */
reg = er32(TARC(0));
- reg &= ~(0xF << 27); /* 30:27 */
+ reg &= ~(0xF << 27); /* 30:27 */
switch (hw->mac.type) {
case e1000_82571:
case e1000_82572:
ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
if (ret_val)
return false;
- if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
+ if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
if (ret_val)
return false;
mac->autoneg = 1;
adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
break;
- case SPEED_1000 + DUPLEX_HALF: /* not supported */
+ case SPEED_1000 + DUPLEX_HALF: /* not supported */
default:
goto err_inval;
}
static int e1000_get_regs_len(struct net_device __always_unused *netdev)
{
-#define E1000_REGS_LEN 32 /* overestimate */
+#define E1000_REGS_LEN 32 /* overestimate */
return E1000_REGS_LEN * sizeof(u32);
}
regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
adapter->pdev->device;
- regs_buff[0] = er32(CTRL);
- regs_buff[1] = er32(STATUS);
+ regs_buff[0] = er32(CTRL);
+ regs_buff[1] = er32(STATUS);
- regs_buff[2] = er32(RCTL);
- regs_buff[3] = er32(RDLEN(0));
- regs_buff[4] = er32(RDH(0));
- regs_buff[5] = er32(RDT(0));
- regs_buff[6] = er32(RDTR);
+ regs_buff[2] = er32(RCTL);
+ regs_buff[3] = er32(RDLEN(0));
+ regs_buff[4] = er32(RDH(0));
+ regs_buff[5] = er32(RDT(0));
+ regs_buff[6] = er32(RDTR);
- regs_buff[7] = er32(TCTL);
- regs_buff[8] = er32(TDLEN(0));
- regs_buff[9] = er32(TDH(0));
+ regs_buff[7] = er32(TCTL);
+ regs_buff[8] = er32(TDLEN(0));
+ regs_buff[9] = er32(TDH(0));
regs_buff[10] = er32(TDT(0));
regs_buff[11] = er32(TIDV);
- regs_buff[12] = adapter->hw.phy.type; /* PHY type (IGP=1, M88=0) */
+ regs_buff[12] = adapter->hw.phy.type; /* PHY type (IGP=1, M88=0) */
/* ethtool doesn't use anything past this point, so all this
* code is likely legacy junk for apps that may or may not exist
if (hw->phy.media_type == e1000_media_type_copper &&
hw->phy.type == e1000_phy_m88) {
- ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
+ ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
} else {
/* Set the ILOS bit on the fiber Nic if half duplex link is
* detected.
ew32(TDT(0), k);
e1e_flush();
msleep(200);
- time = jiffies; /* set the start time for the receive */
+ time = jiffies; /* set the start time for the receive */
good_cnt = 0;
/* receive the sent packets */
do {
*/
} while ((good_cnt < 64) && !time_after(jiffies, time + 20));
if (good_cnt != 64) {
- ret_val = 13; /* ret_val is the same as mis-compare */
+ ret_val = 13; /* ret_val is the same as mis-compare */
break;
}
if (jiffies >= (time + 20)) {
- ret_val = 14; /* error code for time out error */
+ ret_val = 14; /* error code for time out error */
break;
}
}
struct e1000_host_mng_dhcp_cookie {
u32 signature;
- u8 status;
- u8 reserved0;
+ u8 status;
+ u8 reserved0;
u16 vlan_id;
u32 reserved1;
u16 reserved2;
- u8 reserved3;
- u8 checksum;
+ u8 reserved3;
+ u8 checksum;
};
/* Host Interface "Rev 1" */
/* Host Interface "Rev 2" */
struct e1000_host_mng_command_header {
- u8 command_id;
- u8 checksum;
+ u8 command_id;
+ u8 checksum;
u16 reserved1;
u16 reserved2;
u16 command_length;
u32 mta_shadow[MAX_MTA_REG];
u16 rar_entry_count;
- u8 forced_speed_duplex;
+ u8 forced_speed_duplex;
bool adaptive_ifs;
bool has_fwsm;
u32 addr;
u32 id;
- u32 reset_delay_us; /* in usec */
+ u32 reset_delay_us; /* in usec */
u32 revision;
enum e1000_media_type media_type;
};
struct e1000_dev_spec_80003es2lan {
- bool mdic_wa_enable;
+ bool mdic_wa_enable;
};
struct e1000_shadow_ram {
- u16 value;
+ u16 value;
bool modified;
};
void __iomem *hw_addr;
void __iomem *flash_address;
- struct e1000_mac_info mac;
- struct e1000_fc_info fc;
- struct e1000_phy_info phy;
- struct e1000_nvm_info nvm;
- struct e1000_bus_info bus;
+ struct e1000_mac_info mac;
+ struct e1000_fc_info fc;
+ struct e1000_phy_info phy;
+ struct e1000_nvm_info nvm;
+ struct e1000_bus_info bus;
struct e1000_host_mng_dhcp_cookie mng_cookie;
union {
- struct e1000_dev_spec_82571 e82571;
+ struct e1000_dev_spec_82571 e82571;
struct e1000_dev_spec_80003es2lan e80003es2lan;
- struct e1000_dev_spec_ich8lan ich8lan;
+ struct e1000_dev_spec_ich8lan ich8lan;
} dev_spec;
};
/* ICH Flash Protected Region */
union ich8_flash_protected_range {
struct ich8_pr {
- u32 base:13; /* 0:12 Protected Range Base */
- u32 reserved1:2; /* 13:14 Reserved */
- u32 rpe:1; /* 15 Read Protection Enable */
- u32 limit:13; /* 16:28 Protected Range Limit */
- u32 reserved2:2; /* 29:30 Reserved */
- u32 wpe:1; /* 31 Write Protection Enable */
+ u32 base:13; /* 0:12 Protected Range Base */
+ u32 reserved1:2; /* 13:14 Reserved */
+ u32 rpe:1; /* 15 Read Protection Enable */
+ u32 limit:13; /* 16:28 Protected Range Limit */
+ u32 reserved2:2; /* 29:30 Reserved */
+ u32 wpe:1; /* 31 Write Protection Enable */
} range;
u32 regval;
};
struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
- phy->addr = 1;
- phy->reset_delay_us = 100;
-
- phy->ops.set_page = e1000_set_page_igp;
- phy->ops.read_reg = e1000_read_phy_reg_hv;
- phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
- phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
- phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
- phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
- phy->ops.write_reg = e1000_write_phy_reg_hv;
- phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
- phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
- phy->ops.power_up = e1000_power_up_phy_copper;
- phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
- phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+ phy->addr = 1;
+ phy->reset_delay_us = 100;
+
+ phy->ops.set_page = e1000_set_page_igp;
+ phy->ops.read_reg = e1000_read_phy_reg_hv;
+ phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
+ phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
+ phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
+ phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
+ phy->ops.write_reg = e1000_write_phy_reg_hv;
+ phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
+ phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
+ phy->ops.power_up = e1000_power_up_phy_copper;
+ phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
+ phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
phy->id = e1000_phy_unknown;
s32 ret_val;
u16 i = 0;
- phy->addr = 1;
- phy->reset_delay_us = 100;
+ phy->addr = 1;
+ phy->reset_delay_us = 100;
- phy->ops.power_up = e1000_power_up_phy_copper;
- phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
+ phy->ops.power_up = e1000_power_up_phy_copper;
+ phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
/* We may need to do this twice - once for IGP and if that fails,
* we'll set BM func pointers and try again
ret_val = e1000e_determine_phy_address(hw);
if (ret_val) {
phy->ops.write_reg = e1000e_write_phy_reg_bm;
- phy->ops.read_reg = e1000e_read_phy_reg_bm;
+ phy->ops.read_reg = e1000e_read_phy_reg_bm;
ret_val = e1000e_determine_phy_address(hw);
if (ret_val) {
e_dbg("Cannot determine PHY addr. Erroring out\n");
/* Clear shadow ram */
for (i = 0; i < nvm->word_size; i++) {
dev_spec->shadow_ram[i].modified = false;
- dev_spec->shadow_ram[i].value = 0xFFFF;
+ dev_spec->shadow_ram[i].value = 0xFFFF;
}
return 0;
hw->dev_spec.ich8lan.eee_lp_ability = 0;
if (!link)
- return 0; /* No link detected */
+ return 0; /* No link detected */
mac->get_link_status = false;
s32 ret_val = -E1000_ERR_NVM;
u8 count = 0;
- if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
+ if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
return -E1000_ERR_NVM;
flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
* write to bank 0 etc. We also need to erase the segment that
* is going to be written
*/
- ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
+ ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
if (ret_val) {
e_dbg("Could not detect valid bank, assuming bank 0\n");
bank = 0;
{
u32 reg;
u16 data;
- u8 retry = 0;
+ u8 retry = 0;
if (hw->phy.type != e1000_phy_igp_3)
return;
while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
(count < tx_ring->count)) {
bool cleaned = false;
- rmb(); /* read buffer_info after eop_desc */
+ rmb(); /* read buffer_info after eop_desc */
for (; !cleaned; count++) {
tx_desc = E1000_TX_DESC(*tx_ring, i);
buffer_info = &tx_ring->buffer_info[i];
skb_put(skb, l1);
goto copydone;
- } /* if */
+ } /* if */
}
for (j = 0; j < PS_PAGE_BUFFERS; j++) {
u32 rctl, icr = er32(ICR);
if (!icr || test_bit(__E1000_DOWN, &adapter->state))
- return IRQ_NONE; /* Not our interrupt */
+ return IRQ_NONE; /* Not our interrupt */
/* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
* not set, then the adapter didn't send an interrupt
else if ((packets < 5) && (bytes > 512))
retval = low_latency;
break;
- case low_latency: /* 50 usec aka 20000 ints/s */
+ case low_latency: /* 50 usec aka 20000 ints/s */
if (bytes > 10000) {
/* this if handles the TSO accounting */
if (bytes / packets > 8000)
retval = lowest_latency;
}
break;
- case bulk_latency: /* 250 usec aka 4000 ints/s */
+ case bulk_latency: /* 250 usec aka 4000 ints/s */
if (bytes > 25000) {
if (packets > 35)
retval = low_latency;
new_itr = 70000;
break;
case low_latency:
- new_itr = 20000; /* aka hwitr = ~200 */
+ new_itr = 20000; /* aka hwitr = ~200 */
break;
case bulk_latency:
new_itr = 4000;
/* UPE and MPE will be handled by normal PROMISC logic
* in e1000e_set_rx_mode
*/
- rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
- E1000_RCTL_BAM | /* RX All Bcast Pkts */
- E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
+ rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
+ E1000_RCTL_BAM | /* RX All Bcast Pkts */
+ E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
- rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
- E1000_RCTL_DPF | /* Allow filtered pause */
- E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
+ rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
+ E1000_RCTL_DPF | /* Allow filtered pause */
+ E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
/* Do not mess with E1000_CTRL_VME, it affects transmit as well,
* and that breaks VLANs.
*/
hwm = min(((pba << 10) * 9 / 10),
((pba << 10) - adapter->max_frame_size));
- fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
+ fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
fc->low_water = fc->high_water - 8;
break;
case e1000_pchlan:
*/
if (adapter->netdev->mtu > ETH_DATA_LEN) {
fc->high_water = 0x3500;
- fc->low_water = 0x1500;
+ fc->low_water = 0x1500;
} else {
fc->high_water = 0x5000;
- fc->low_water = 0x3000;
+ fc->low_water = 0x3000;
}
fc->refresh_time = 0x1000;
break;
adapter->stats.crcerrs += er32(CRCERRS);
adapter->stats.gprc += er32(GPRC);
adapter->stats.gorc += er32(GORCL);
- er32(GORCH); /* Clear gorc */
+ er32(GORCH); /* Clear gorc */
adapter->stats.bprc += er32(BPRC);
adapter->stats.mprc += er32(MPRC);
adapter->stats.roc += er32(ROC);
adapter->stats.xofftxc += er32(XOFFTXC);
adapter->stats.gptc += er32(GPTC);
adapter->stats.gotc += er32(GOTCL);
- er32(GOTCH); /* Clear gotc */
+ er32(GOTCH); /* Clear gotc */
adapter->stats.rnbc += er32(RNBC);
adapter->stats.ruc += er32(RUC);
context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
buffer_info = &tx_ring->buffer_info[i];
- context_desc->lower_setup.ip_fields.ipcss = ipcss;
- context_desc->lower_setup.ip_fields.ipcso = ipcso;
- context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
+ context_desc->lower_setup.ip_fields.ipcss = ipcss;
+ context_desc->lower_setup.ip_fields.ipcso = ipcso;
+ context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
context_desc->upper_setup.tcp_fields.tucss = tucss;
context_desc->upper_setup.tcp_fields.tucso = tucso;
context_desc->upper_setup.tcp_fields.tucse = 0;
- context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
+ context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
context_desc->cmd_and_length = cpu_to_le32(cmd_length);
static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
struct sk_buff *skb)
{
- struct e1000_hw *hw = &adapter->hw;
+ struct e1000_hw *hw = &adapter->hw;
u16 length, offset;
if (vlan_tx_tag_present(skb) &&
e1000_intr_msi(adapter->pdev->irq, netdev);
enable_irq(adapter->pdev->irq);
break;
- default: /* E1000E_INT_MODE_LEGACY */
+ default: /* E1000E_INT_MODE_LEGACY */
disable_irq(adapter->pdev->irq);
e1000_intr(adapter->pdev->irq, netdev);
enable_irq(adapter->pdev->irq);
adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
/* construct the net_device struct */
- netdev->netdev_ops = &e1000e_netdev_ops;
+ netdev->netdev_ops = &e1000e_netdev_ops;
e1000e_set_ethtool_ops(netdev);
- netdev->watchdog_timeo = 5 * HZ;
+ netdev->watchdog_timeo = 5 * HZ;
netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
}
module_exit(e1000_exit_module);
-
MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
MODULE_LICENSE("GPL");
u16 data;
eecd = er32(EECD);
-
eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
data = 0;
case e1000_phy_gg82563:
case e1000_phy_bm:
case e1000_phy_82578:
- offset = M88E1000_PHY_SPEC_STATUS;
- mask = M88E1000_PSSR_DOWNSHIFT;
+ offset = M88E1000_PHY_SPEC_STATUS;
+ mask = M88E1000_PSSR_DOWNSHIFT;
break;
case e1000_phy_igp_2:
case e1000_phy_igp_3:
- offset = IGP01E1000_PHY_LINK_HEALTH;
- mask = IGP01E1000_PLHR_SS_DOWNGRADE;
+ offset = IGP01E1000_PHY_LINK_HEALTH;
+ mask = IGP01E1000_PLHR_SS_DOWNGRADE;
break;
default:
/* speed downshift not supported */
if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
IGP01E1000_PSSR_SPEED_1000MBPS) {
- offset = IGP01E1000_PHY_PCS_INIT_REG;
- mask = IGP01E1000_PHY_POLARITY_MASK;
+ offset = IGP01E1000_PHY_PCS_INIT_REG;
+ mask = IGP01E1000_PHY_POLARITY_MASK;
} else {
/* This really only applies to 10Mbps since
* there is no polarity for 100Mbps (always 0).
*/
- offset = IGP01E1000_PHY_PORT_STATUS;
- mask = IGP01E1000_PSSR_POLARITY_REVERSED;
+ offset = IGP01E1000_PHY_PORT_STATUS;
+ mask = IGP01E1000_PSSR_POLARITY_REVERSED;
}
ret_val = e1e_rphy(hw, offset, &data);
s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
{
struct e1000_phy_info *phy = &hw->phy;
- s32 ret_val;
+ s32 ret_val;
u16 phy_data;
bool link;
case M88E1011_I_PHY_ID:
phy_type = e1000_phy_m88;
break;
- case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
+ case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
phy_type = e1000_phy_igp_2;
break;
case GG82563_E_PHY_ID:
/* If phy_type is valid, break - we found our
* PHY address
*/
- if (phy_type != e1000_phy_unknown)
+ if (phy_type != e1000_phy_unknown)
return 0;
usleep_range(1000, 2000);
projects / platform / kernel / linux-exynos.git / commitdiff