target-sparc: fix FMOVr instruction

Like the MOVr instruction, the FMOVr instruction has the condition
encoded between bits 10 and 12.

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 5df2876..4321393 100644 (file)
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -3176,7 +3176,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
 #define FMOVR(sz)                                                  \
                 do {                                               \
                     DisasCompare cmp;                              \
-                    cond = GET_FIELD_SP(insn, 14, 17);             \
+                    cond = GET_FIELD_SP(insn, 10, 12);             \
                     cpu_src1 = get_src1(dc, insn);                 \
                     gen_compare_reg(&cmp, cond, cpu_src1);         \
                     gen_fmov##sz(dc, &cmp, rd, rs2);               \