powerpc: mpc83xx: remove board support for MERGERBOX and MVBLM7
authorMasahiro Yamada <yamada.m@jp.panasonic.com>
Sun, 28 Sep 2014 16:38:00 +0000 (01:38 +0900)
committerTom Rini <trini@ti.com>
Fri, 10 Oct 2014 13:44:43 +0000 (09:44 -0400)
These boards have been orphaned for more than 6 months.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
27 files changed:
arch/powerpc/cpu/mpc83xx/Kconfig
board/matrix_vision/mergerbox/Kconfig [deleted file]
board/matrix_vision/mergerbox/MAINTAINERS [deleted file]
board/matrix_vision/mergerbox/Makefile [deleted file]
board/matrix_vision/mergerbox/README [deleted file]
board/matrix_vision/mergerbox/fpga.c [deleted file]
board/matrix_vision/mergerbox/fpga.h [deleted file]
board/matrix_vision/mergerbox/mergerbox.c [deleted file]
board/matrix_vision/mergerbox/mergerbox.h [deleted file]
board/matrix_vision/mergerbox/pci.c [deleted file]
board/matrix_vision/mergerbox/sm107.c [deleted file]
board/matrix_vision/mvblm7/.gitignore [deleted file]
board/matrix_vision/mvblm7/Kconfig [deleted file]
board/matrix_vision/mvblm7/MAINTAINERS [deleted file]
board/matrix_vision/mvblm7/Makefile [deleted file]
board/matrix_vision/mvblm7/README.mvblm7 [deleted file]
board/matrix_vision/mvblm7/bootscript [deleted file]
board/matrix_vision/mvblm7/fpga.c [deleted file]
board/matrix_vision/mvblm7/fpga.h [deleted file]
board/matrix_vision/mvblm7/mvblm7.c [deleted file]
board/matrix_vision/mvblm7/mvblm7.h [deleted file]
board/matrix_vision/mvblm7/pci.c [deleted file]
configs/MERGERBOX_defconfig [deleted file]
configs/MVBLM7_defconfig [deleted file]
doc/README.scrapyard
include/configs/MERGERBOX.h [deleted file]
include/configs/MVBLM7.h [deleted file]

index 6de9265..42e0e29 100644 (file)
@@ -64,12 +64,6 @@ config TARGET_SUVD3
 config TARGET_TUXX1
        bool "Support tuxx1"
 
-config TARGET_MERGERBOX
-       bool "Support MERGERBOX"
-
-config TARGET_MVBLM7
-       bool "Support MVBLM7"
-
 config TARGET_TQM834X
        bool "Support TQM834x"
 
@@ -89,8 +83,6 @@ source "board/freescale/mpc837xemds/Kconfig"
 source "board/freescale/mpc837xerdb/Kconfig"
 source "board/ids/ids8313/Kconfig"
 source "board/keymile/km83xx/Kconfig"
-source "board/matrix_vision/mergerbox/Kconfig"
-source "board/matrix_vision/mvblm7/Kconfig"
 source "board/mpc8308_p1m/Kconfig"
 source "board/sbc8349/Kconfig"
 source "board/tqc/tqm834x/Kconfig"
diff --git a/board/matrix_vision/mergerbox/Kconfig b/board/matrix_vision/mergerbox/Kconfig
deleted file mode 100644 (file)
index 3857535..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MERGERBOX
-
-config SYS_BOARD
-       default "mergerbox"
-
-config SYS_VENDOR
-       default "matrix_vision"
-
-config SYS_CONFIG_NAME
-       default "MERGERBOX"
-
-endif
diff --git a/board/matrix_vision/mergerbox/MAINTAINERS b/board/matrix_vision/mergerbox/MAINTAINERS
deleted file mode 100644 (file)
index 20bd073..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-MERGERBOX BOARD
-#M:    Andre Schwarz <andre.schwarz@matrix-vision.de>
-S:     Orphan (since 2014-03)
-F:     board/matrix_vision/mergerbox/
-F:     include/configs/MERGERBOX.h
-F:     configs/MERGERBOX_defconfig
diff --git a/board/matrix_vision/mergerbox/Makefile b/board/matrix_vision/mergerbox/Makefile
deleted file mode 100644 (file)
index 11a7fd2..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y += mergerbox.o pci.o fpga.o sm107.o
diff --git a/board/matrix_vision/mergerbox/README b/board/matrix_vision/mergerbox/README
deleted file mode 100644 (file)
index 1994b65..0000000
+++ /dev/null
@@ -1,59 +0,0 @@
-Matrix Vision MergerBox
------------------------
-
-1.     Board Description
-
-       The MergerBox is a 120x160mm single board computing platform
-       for 3D Full-HD digital video processing.
-
-       Power Supply is 10-32VDC.
-
-2      System Components
-
-2.1    CPU
-       Freescale MPC8377 CPU running at 800MHz core and 333MHz csb.
-       256 MByte DDR-II memory @ 333MHz data rate.
-       64 MByte Nor Flash on local bus.
-       1 GByte Nand Flash on FCM.
-       1 Vitesse VSC8601 RGMII ethernet Phys.
-       1 USB host controller over ULPI I/F with 4-Port hub.
-       2 serial ports. Console running on ttyS0 @ 115200 8N1.
-       1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt.
-       2 PCIe x1 busses on local mPCIe and cutom expansion connector.
-       2 SATA host ports.
-       System configuration (HRCW) is taken from I2C EEPROM.
-
-2.2    Graphics
-       SM107 emebedded video controller driving a 5" 800x480 TFT panel.
-       Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory.
-
-2.3    FPGA
-       Altera Cyclone-IV EP4C115 with several PCI DMA engines.
-       Connects to 7x Gennum 3G-SDI transceivers as video interconnect
-       as well as a HDMI v1.4 compliant output for 3D monitoring.
-       Utilizes two more DDR-II controllers providing 256MB memory.
-
-2.4    I2C
-       Bus1:
-               AD7418 @ 0x50 for voltage/temp. monitoring.
-               SX8650 @ 0x90 touch controller for HMI.
-               EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
-       Bus2:
-               mPCIe SMBus
-               SiI9022A @ 0x72/0xC0 HDMI transmitter.
-               TCA6416A @ 0x40 + 0x42 16-Bit I/O expander.
-               LMH1983 @ 0xCA video PLL.
-               DS1338C @ 0xD0 real-time clock with embedded crystal.
-               9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock.
-
-3      Flash layout.
-
-       reset vector is 0x00000100, i.e. low boot.
-
-       00000000        u-boot binary.
-       00100000        FPGA raw bit file.
-       00300000        FIT image holding kernel, dtb and rescue squashfs.
-       03d00000        u-boot environment.
-       03e00000        splash image
-
-       mtd partitions are propagated to linux kernel via device tree blob.
diff --git a/board/matrix_vision/mergerbox/fpga.c b/board/matrix_vision/mergerbox/fpga.c
deleted file mode 100644 (file)
index 57552c1..0000000
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * (C) Copyright 2011
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <ACEX1K.h>
-#include <command.h>
-#include "mergerbox.h"
-#include "fpga.h"
-
-Altera_CYC2_Passive_Serial_fns altera_fns = {
-       fpga_null_fn,
-       fpga_config_fn,
-       fpga_status_fn,
-       fpga_done_fn,
-       fpga_wr_fn,
-       fpga_null_fn,
-       fpga_null_fn,
-};
-
-Altera_desc cyclone2 = {
-       Altera_CYC2,
-       passive_serial,
-       Altera_EP2C20_SIZE,
-       (void *) &altera_fns,
-       NULL,
-       0
-};
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int mergerbox_init_fpga(void)
-{
-       debug("Initialize FPGA interface\n");
-       fpga_init();
-       fpga_add(fpga_altera, &cyclone2);
-
-       return 1;
-}
-
-int fpga_null_fn(int cookie)
-{
-       return 0;
-}
-
-int fpga_config_fn(int assert, int flush, int cookie)
-{
-       volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-       volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
-       u32 dvo = gpio->dat;
-
-       dvo &= ~FPGA_CONFIG;
-       gpio->dat = dvo;
-       udelay(5);
-       dvo |= FPGA_CONFIG;
-       gpio->dat = dvo;
-
-       return assert;
-}
-
-int fpga_done_fn(int cookie)
-{
-       volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-       volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
-       int result = 0;
-
-       udelay(10);
-       debug("CONF_DONE check ... ");
-       if (gpio->dat & FPGA_CONF_DONE) {
-               debug("high\n");
-               result = 1;
-       } else
-               debug("low\n");
-
-       return result;
-}
-
-int fpga_status_fn(int cookie)
-{
-       volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-       volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
-       int result = 0;
-
-       debug("STATUS check ... ");
-       if (gpio->dat & FPGA_STATUS) {
-               debug("high\n");
-               result = 1;
-       } else
-               debug("low\n");
-
-       return result;
-}
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-       volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-       volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
-       u32 dvo = gpio->dat;
-
-       debug("CLOCK %s\n", assert_clk ? "high" : "low");
-       if (assert_clk)
-               dvo |= FPGA_CCLK;
-       else
-               dvo &= ~FPGA_CCLK;
-
-       if (flush)
-               gpio->dat = dvo;
-
-       return assert_clk;
-}
-
-static inline int _write_fpga(u8 val, int dump)
-{
-       volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-       volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0];
-       int i;
-       u32 dvo = gpio->dat;
-
-       if (dump)
-               debug("  %02x -> ", val);
-       for (i = 0; i < 8; i++) {
-               dvo &= ~FPGA_CCLK;
-               gpio->dat = dvo;
-               dvo &= ~FPGA_DIN;
-               if (dump)
-                       debug("%d ", val&1);
-               if (val & 1)
-                       dvo |= FPGA_DIN;
-               gpio->dat = dvo;
-               dvo |= FPGA_CCLK;
-               gpio->dat = dvo;
-               val >>= 1;
-       }
-       if (dump)
-               debug("\n");
-
-       return 0;
-}
-
-int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
-{
-       unsigned char *data = (unsigned char *) buf;
-       int i;
-
-       debug("fpga_wr: buf %p / size %d\n", buf, len);
-       for (i = 0; i < len; i++)
-               _write_fpga(data[i], 0);
-       debug("\n");
-
-       return FPGA_SUCCESS;
-}
diff --git a/board/matrix_vision/mergerbox/fpga.h b/board/matrix_vision/mergerbox/fpga.h
deleted file mode 100644 (file)
index dbe9bff..0000000
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-extern int mergerbox_init_fpga(void);
-
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_status_fn(int cookie);
-extern int fpga_config_fn(int assert, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
-extern int fpga_null_fn(int cookie);
diff --git a/board/matrix_vision/mergerbox/mergerbox.c b/board/matrix_vision/mergerbox/mergerbox.c
deleted file mode 100644 (file)
index 5c891d1..0000000
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <spi.h>
-#include <asm/io.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-#include <fdt_support.h>
-#include <spd_sdram.h>
-#include "mergerbox.h"
-#include "fpga.h"
-#include "../common/mv_common.h"
-
-static void setup_serdes(void)
-{
-       fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
-               FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-       fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
-               FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-}
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram(void)
-{
-       uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
-       uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
-       uint *p;
-
-       printf("Testing DRAM from 0x%08x to 0x%08x\n",
-               CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
-
-       printf("DRAM test phase 1:\n");
-       for (p = pstart; p < pend; p++)
-               *p = 0xaaaaaaaa;
-
-       for (p = pstart; p < pend; p++) {
-               if (*p != 0xaaaaaaaa) {
-                       printf("DRAM test fails at: %08x\n", (uint) p);
-                       return 1;
-               }
-       }
-
-       printf("DRAM test phase 2:\n");
-       for (p = pstart; p < pend; p++)
-               *p = 0x55555555;
-
-       for (p = pstart; p < pend; p++) {
-               if (*p != 0x55555555) {
-                       printf("DRAM test fails at: %08x\n", (uint) p);
-                       return 1;
-               }
-       }
-
-       printf("DRAM test passed.\n");
-       return 0;
-}
-#endif
-
-phys_size_t initdram(int board_type)
-{
-       u32 msize;
-
-       volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-       volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk;
-
-       /* Enable PCI_CLK[0:1] */
-       clk->occr |= 0xc0000000;
-       udelay(2000);
-
-#if defined(CONFIG_SPD_EEPROM)
-       msize = spd_sdram();
-#else
-       immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-       u32 msize_log2;
-
-       msize = CONFIG_SYS_DDR_SIZE;
-       msize_log2 = __ilog2(msize);
-
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
-       im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-
-       im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-       udelay(50000);
-
-       im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
-       udelay(1000);
-
-       im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
-       im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-       udelay(1000);
-
-       im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-       im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-       im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-       im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-       im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-       im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-       im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-       im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-       im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-       __asm__ __volatile__("sync");
-       udelay(1000);
-
-       im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-       udelay(2000);
-#endif
-       setup_serdes();
-
-       return msize << 20;
-}
-
-int checkboard(void)
-{
-       puts("Board: Matrix Vision MergerBox\n");
-
-       return 0;
-}
-
-int misc_init_r(void)
-{
-       u16 dim;
-       int result;
-       volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-       volatile gpio83xx_t *gpio = (gpio83xx_t *)&immr->gpio[1];
-       unsigned char mac[6], mac_verify[6];
-       char *s = getenv("reset_env");
-
-       for (dim = 10; dim < 180; dim += 5) {
-               mergerbox_tft_dim(dim);
-               udelay(100000);
-       }
-
-       if (s)
-               mv_reset_environment();
-
-       i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac, sizeof(mac));
-
-       /* check if Matrix Vision prefix present and export to env */
-       if (mac[0] == 0x00 && mac[1] == 0x0c && mac[2] == 0x8d) {
-               printf("valid MAC found in eeprom: %pM\n", mac);
-               eth_setenv_enetaddr("ethaddr", mac);
-       } else {
-               printf("no valid MAC found in eeprom.\n");
-
-               /* no: check the env */
-               if (!eth_getenv_enetaddr("ethaddr", mac)) {
-                       printf("no valid MAC found in env either.\n");
-                       /* TODO: ask for valid MAC */
-               } else {
-                       printf("valid MAC found in env: %pM\n", mac);
-                       printf("updating MAC in eeprom.\n");
-
-                       do {
-                               result = test_and_clear_bit(20, &gpio->dat);
-                               if (result)
-                                       printf("unprotect EEPROM failed !\n");
-                               udelay(20000);
-                       } while(result);
-
-                       i2c_write(SPD_EEPROM_ADDRESS, 0x80, 2, mac, 6);
-                       udelay(20000);
-
-                       do {
-                               result = test_and_set_bit(20, &gpio->dat);
-                               if (result)
-                                       printf("protect EEPROM failed !\n");
-                               udelay(20000);
-                       } while(result);
-
-                       printf("verify MAC %pM ... ", mac);
-                       i2c_read(SPD_EEPROM_ADDRESS, 0x80, 2, mac_verify, 6);
-
-                       if (!strncmp((char *)mac, (char *)mac_verify, 6))
-                               printf("ok.\n");
-                       else
-                               /* TODO: retry or do something useful */
-                               printf("FAILED (got %pM) !\n", mac_verify);
-               }
-       }
-
-       return 0;
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-       return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-       volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
-       iopd->dat &= ~TFT_SPI_CPLD_CS;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-       volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
-       iopd->dat |= TFT_SPI_CPLD_CS;
-}
-
-/* control backlight pwm (display brightness).
- * allow values 0-250 with 0 = turn off and 250 = max brightness
- */
-void mergerbox_tft_dim(u16 value)
-{
-       struct spi_slave *slave;
-       u16 din;
-       u16 dout = 0;
-
-       if (value > 0 && value < 250)
-               dout = 0x4000 | value;
-
-       slave = spi_setup_slave(0, 0, 1000000, SPI_MODE_0 | SPI_CS_HIGH);
-       spi_claim_bus(slave);
-       spi_xfer(slave, 16, &dout, &din, SPI_XFER_BEGIN | SPI_XFER_END);
-       spi_release_bus(slave);
-       spi_free_slave(slave);
-}
-
-void ft_board_setup(void *blob, bd_t *bd)
-{
-       ft_cpu_setup(blob, bd);
-       fdt_fixup_dr_usb(blob, bd);
-       ft_pci_setup(blob, bd);
-}
diff --git a/board/matrix_vision/mergerbox/mergerbox.h b/board/matrix_vision/mergerbox/mergerbox.h
deleted file mode 100644 (file)
index 53eab28..0000000
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef __MERGERBOX_H__
-#define __MERGERBOX_H__
-
-#define MV_GPIO
-
-/*
- * GPIO Bank 1
- */
-#define        TFT_SPI_EN      (0x80000000>>0)
-#define        FPGA_CONFIG     (0x80000000>>1)
-#define        FPGA_STATUS     (0x80000000>>2)
-#define        FPGA_CONF_DONE  (0x80000000>>3)
-#define        FPGA_DIN        (0x80000000>>4)
-#define        FPGA_CCLK       (0x80000000>>5)
-#define        MAN_RST         (0x80000000>>6)
-#define        FPGA_SYS_RST    (0x80000000>>7)
-#define        WD_WDI          (0x80000000>>8)
-#define        TFT_RST         (0x80000000>>9)
-#define        HISCON_GPIO1    (0x80000000>>10)
-#define        HISCON_GPIO2    (0x80000000>>11)
-#define        B2B_GPIO2       (0x80000000>>12)
-#define        CCU_GPIN        (0x80000000>>13)
-#define        CCU_GPOUT       (0x80000000>>14)
-#define        TFT_GPIO0       (0x80000000>>15)
-#define        TFT_GPIO1       (0x80000000>>16)
-#define        TFT_GPIO2       (0x80000000>>17)
-#define        TFT_GPIO3       (0x80000000>>18)
-#define        B2B_GPIO0       (0x80000000>>19)
-#define        B2B_GPIO1       (0x80000000>>20)
-#define        TFT_SPI_CPLD_CS (0x80000000>>21)
-#define        TFT_SPI_CS      (0x80000000>>22)
-#define        CCU_PWR_EN      (0x80000000>>23)
-#define        B2B_GPIO3       (0x80000000>>24)
-#define        CCU_PWR_STAT    (0x80000000>>25)
-
-#define MV_GPIO1_DAT   (FPGA_CONFIG|CCU_PWR_EN|TFT_SPI_CPLD_CS)
-#define MV_GPIO1_OUT   (TFT_SPI_EN|FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|CCU_PWR_EN| \
-                        TFT_SPI_CPLD_CS)
-#define MV_GPIO1_ODE   (FPGA_CONFIG|MAN_RST)
-
-/*
- * GPIO Bank 2
- */
-#define        SPI_FLASH_WP    (0x80000000>>10)
-#define        SYS_EEPROM_WP   (0x80000000>>11)
-#define        SPI_FLASH_CS    (0x80000000>>22)
-
-#define MV_GPIO2_DAT   (SYS_EEPROM_WP|SPI_FLASH_CS)
-#define MV_GPIO2_OUT   (SPI_FLASH_WP|SYS_EEPROM_WP|SPI_FLASH_CS)
-#define MV_GPIO2_ODE   0
-
-void mergerbox_tft_dim(u16 value);
-
-#endif
diff --git a/board/matrix_vision/mergerbox/pci.c b/board/matrix_vision/mergerbox/pci.c
deleted file mode 100644 (file)
index 480f3ed..0000000
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-#include "mergerbox.h"
-#include "fpga.h"
-#include "../common/mv_common.h"
-
-static struct pci_region pci_regions[] = {
-       {
-               .bus_start = CONFIG_SYS_PCI_MEM_BASE,
-               .phys_start = CONFIG_SYS_PCI_MEM_PHYS,
-               .size = CONFIG_SYS_PCI_MEM_SIZE,
-               .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
-       },
-       {
-               .bus_start = CONFIG_SYS_PCI_MMIO_BASE,
-               .phys_start = CONFIG_SYS_PCI_MMIO_PHYS,
-               .size = CONFIG_SYS_PCI_MMIO_SIZE,
-               .flags = PCI_REGION_MEM
-       },
-       {
-               .bus_start = CONFIG_SYS_PCI_IO_BASE,
-               .phys_start = CONFIG_SYS_PCI_IO_PHYS,
-               .size = CONFIG_SYS_PCI_IO_SIZE,
-               .flags = PCI_REGION_IO
-       }
-};
-
-static struct pci_region pcie_regions_0[] = {
-       {
-               .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
-               .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
-               .size = CONFIG_SYS_PCIE1_MEM_SIZE,
-               .flags = PCI_REGION_MEM,
-       },
-       {
-               .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
-               .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
-               .size = CONFIG_SYS_PCIE1_IO_SIZE,
-               .flags = PCI_REGION_IO,
-       },
-};
-
-static struct pci_region pcie_regions_1[] = {
-       {
-               .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
-               .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
-               .size = CONFIG_SYS_PCIE2_MEM_SIZE,
-               .flags = PCI_REGION_MEM,
-       },
-       {
-               .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
-               .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
-               .size = CONFIG_SYS_PCIE2_IO_SIZE,
-               .flags = PCI_REGION_IO,
-       },
-};
-
-void pci_init_board(void)
-{
-       volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-       volatile sysconf83xx_t *sysconf = &immr->sysconf;
-       volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk;
-       volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-       volatile law83xx_t *pcie_law = sysconf->pcielaw;
-       struct pci_region *reg[] = { pci_regions };
-       struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
-
-       volatile gpio83xx_t *gpio;
-       gpio = (gpio83xx_t *)&immr->gpio[0];
-
-       gpio->dat = MV_GPIO1_DAT;
-       gpio->odr = MV_GPIO1_ODE;
-       gpio->dir = MV_GPIO1_OUT;
-
-       gpio = (gpio83xx_t *)&immr->gpio[1];
-
-       gpio->dat = MV_GPIO2_DAT;
-       gpio->odr = MV_GPIO2_ODE;
-       gpio->dir = MV_GPIO2_OUT;
-
-       printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
-               immr->sysconf.sicrl);
-
-       /* Enable PCI_CLK[0:1] */
-       clk->occr |= 0xc0000000;
-       udelay(2000);
-
-       mergerbox_init_fpga();
-       mv_load_fpga();
-
-       mergerbox_tft_dim(0);
-
-       /* Configure PCI Local Access Windows */
-       pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
-       pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-       pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
-       pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-       udelay(2000);
-
-       mpc83xx_pci_init(1, reg);
-
-       /* Deassert the resets in the control register */
-       out_be32(&sysconf->pecr1, 0xE0008000);
-       out_be32(&sysconf->pecr2, 0xE0008000);
-       udelay(2000);
-
-       out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
-       out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-       out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
-       out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-       mpc83xx_pcie_init(2, pcie_reg);
-}
diff --git a/board/matrix_vision/mergerbox/sm107.c b/board/matrix_vision/mergerbox/sm107.c
deleted file mode 100644 (file)
index d24f926..0000000
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <netdev.h>
-#include <sm501.h>
-#include <pci.h>
-#include "../common/mv_common.h"
-
-#ifdef CONFIG_VIDEO
-static const SMI_REGS init_regs_800x480[] = {
-       /* set endianess to little endian */
-       {0x0005c, 0x00000000},
-       /* PCI drive 12mA */
-       {0x00004, 0x42401001},
-       /* current clock */
-       {0x0003c, 0x310a1818},
-       /* clocks for pm0... */
-       {0x00040, 0x0002184f},
-       {0x00044, 0x2a1a0a01},
-       /* GPIO */
-       {0x10008, 0x00000000},
-       {0x1000C, 0x00000000},
-       /* panel control regs */
-       {0x80000, 0x0f017106},
-       {0x80004, 0x0},
-       {0x80008, 0x0},
-       {0x8000C, 0x00000000},
-       {0x80010, 0x0c800c80},
-       /* width 0x320 */
-       {0x80014, 0x03200000},
-       /* height 0x1e0 */
-       {0x80018, 0x01E00000},
-       {0x8001C, 0x0},
-       {0x80020, 0x01df031f},
-       {0x80024, 0x041f031f},
-       {0x80028, 0x00800347},
-       {0x8002C, 0x020c01df},
-       {0x80030, 0x000201e9},
-       {0x80200, 0x00000000},
-       /* ZV[0:7] */
-       {0x00008, 0x00ff0000},
-       /* 24-Bit TFT */
-       {0x0000c, 0x3f000000},
-       {0, 0}
-};
-
-/*
- * Returns SM107 register base address. First thing called in the driver.
- */
-unsigned int board_video_init(void)
-{
-       pci_dev_t devbusfn;
-       u32 addr;
-
-       devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
-       if (devbusfn != -1) {
-               pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1,
-                       (u32 *)&addr);
-               return addr & 0xfffffffe;
-       }
-
-       return 0;
-}
-
-/*
- * Called after initializing the SM501 and before clearing the screen.
- */
-void board_validate_screen(unsigned int base)
-{
-}
-
-/*
- * Returns SM107 framebuffer address
- */
-unsigned int board_video_get_fb(void)
-{
-       pci_dev_t devbusfn;
-       u32 addr;
-
-       devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
-       if (devbusfn != -1) {
-               pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
-                       (u32 *)&addr);
-               addr &= 0xfffffffe;
-#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
-               addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
-#endif
-               return addr;
-       }
-
-       printf("board_video_get_fb(): FAILED\n");
-
-       return 0;
-}
-
-/*
- * Return a pointer to the initialization sequence.
- */
-const SMI_REGS *board_get_regs(void)
-{
-       return init_regs_800x480;
-}
-
-int board_get_width(void)
-{
-       return 800;
-}
-
-int board_get_height(void)
-{
-       return 480;
-}
-#endif
diff --git a/board/matrix_vision/mvblm7/.gitignore b/board/matrix_vision/mvblm7/.gitignore
deleted file mode 100644 (file)
index 469f1bc..0000000
+++ /dev/null
@@ -1 +0,0 @@
-bootscript.img
diff --git a/board/matrix_vision/mvblm7/Kconfig b/board/matrix_vision/mvblm7/Kconfig
deleted file mode 100644 (file)
index ea7a6f8..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MVBLM7
-
-config SYS_BOARD
-       default "mvblm7"
-
-config SYS_VENDOR
-       default "matrix_vision"
-
-config SYS_CONFIG_NAME
-       default "MVBLM7"
-
-endif
diff --git a/board/matrix_vision/mvblm7/MAINTAINERS b/board/matrix_vision/mvblm7/MAINTAINERS
deleted file mode 100644 (file)
index 947a14e..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-MVBLM7 BOARD
-#M:    Andre Schwarz <andre.schwarz@matrix-vision.de>
-S:     Orphan (since 2014-03)
-F:     board/matrix_vision/mvblm7/
-F:     include/configs/MVBLM7.h
-F:     configs/MVBLM7_defconfig
diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile
deleted file mode 100644 (file)
index caa6cfd..0000000
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Copyright (C) Freescale Semiconductor, Inc. 2006.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  := mvblm7.o pci.o fpga.o
-
-extra-y := bootscript.img
-
-MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script
-
-$(obj)/bootscript.img: $(src)/bootscript
-       $(call cmd,mkimage)
diff --git a/board/matrix_vision/mvblm7/README.mvblm7 b/board/matrix_vision/mvblm7/README.mvblm7
deleted file mode 100644 (file)
index a0686f7..0000000
+++ /dev/null
@@ -1,84 +0,0 @@
-Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
--------------------------------------
-
-1.     Board Description
-
-       The mvBL-M7 is a 120x120mm single board computing platform
-       with strong focus on stereo image processing applications.
-
-       Power Supply is either VDC 12-48V or Pover over Ethernet (PoE)
-       on any port (requires add-on board).
-
-2      System Components
-
-2.1    CPU
-       Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
-       512MByte DDR-II memory @ 133MHz.
-       8 MByte Nor Flash on local bus.
-       2 Vitesse VSC8601 RGMII ethernet Phys.
-       1 USB host controller over ULPI I/F.
-       2 serial ports. Console running on ttyS0 @ 115200 8N1.
-       1 SD-Card slot connected to SPI.
-       System configuration (HRCW) is taken from I2C EEPROM.
-
-2.2    PCI
-       A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.
-
-2.3    FPGA
-       Altera Cyclone-II EP2C20/35 with PCI DMA engines.
-       Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
-       Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash.
-
-2.3.1  I/O @ FPGA
-       2x8 Outputs : Infineon High-Side Switches to Main Supply.
-       2x8 Inputs  : Programmable input threshold + trigger capabilities
-       2 dedicated flash interfaces for illuminator boards.
-       Cross trigger for chaining several boards.
-
-2.4    I2C
-       Bus1:
-               MAX5381 DAC @ 0x60 for 1st digital input threshold.
-               LM75 @ 0x90 for temperature monitoring.
-               EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
-               1st image sensor interface (slave addresses depend on sensor)
-       Bus2:
-               MAX5381 DAC @ 0x60 for 2nd digital input threshold.
-               2nd image sensor interface (slave addresses depend on sensor)
-
-3      Flash layout.
-
-       reset vector is 0xFFF00100, i.e. "HIGHBOOT".
-
-       FF800000        environment
-       FF802000        redundant environment
-       FF804000        u-boot script image
-       FF806000        redundant u-boot script image
-       FF808000        device tree blob
-       FF80A000        redundant device tree blob
-       FF80C000        tbd.
-       FF80E000        tbd.
-       FF810000        kernel
-       FFC00000        root FS
-       FFF00000        u-boot
-       FFF80000        FPGA raw bit file
-
-       mtd partitions are propagated to linux kernel via device tree blob.
-
-4      Booting
-
-       On startup the bootscript @ FF804000 is executed. This script can be
-       exchanged easily. Default boot mode is "boot from flash", i.e. system
-       works stand-alone.
-
-       This behaviour depends on some environment variables :
-
-       "netboot" : yes ->try dhcp/bootp and boot from network.
-       A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
-       DHCP server configuration, e.g. to provide different images to
-       different devices.
-
-       During netboot the system tries to get 3 image files:
-       1. Kernel - name + data is given during BOOTP.
-       2. Initrd - name is stored in "initrd_name"
-       3. device tree blob - name is stored in "dtb_name"
-       Fallback files are the flash versions.
diff --git a/board/matrix_vision/mvblm7/bootscript b/board/matrix_vision/mvblm7/bootscript
deleted file mode 100644 (file)
index dc385fd..0000000
+++ /dev/null
@@ -1,43 +0,0 @@
-echo
-echo "==== running autoscript ===="
-echo
-setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
-setenv ramkernel setenv kernel_boot \${loadaddr}
-setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
-setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
-setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb
-setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
-setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
-setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
-setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
-if test ${console} = yes;
-then
-setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8
-else
-setenv addcons setenv bootargs \${bootargs} console=tty0
-fi
-setenv set_static_ip setenv ipaddr \${static_ipaddr}
-setenv set_static_nm setenv netmask \${static_netmask}
-setenv set_static_gw setenv gatewayip \${static_gateway}
-setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
-setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
-if test ${autoscript_boot} != no;
-then
-  if test ${netboot} = yes;
-  then
-    bootp
-    if test $? = 0;
-    then
-      echo "=== bootp succeeded -> netboot ==="
-      run set_ip
-      run getdtb rundtb bootfromnet ramparam addcons bootdtb
-    else
-      echo "=== netboot failed ==="
-    fi
-  fi
-  run set_static_ip set_static_nm set_static_gw set_ip
-  echo "=== bootfromflash ==="
-  run cpdtb rundtb bootfromflash
-else
-  echo "=== boot stopped with autoscript_boot no ==="
-fi
diff --git a/board/matrix_vision/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c
deleted file mode 100644 (file)
index c0c5bed..0000000
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <ACEX1K.h>
-#include <command.h>
-#include "fpga.h"
-#include "mvblm7.h"
-
-#ifdef FPGA_DEBUG
-#define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
-#else
-#define fpga_debug(fmt, args...)
-#endif
-
-Altera_CYC2_Passive_Serial_fns altera_fns = {
-       fpga_null_fn,
-       fpga_config_fn,
-       fpga_status_fn,
-       fpga_done_fn,
-       fpga_wr_fn,
-       fpga_null_fn,
-       fpga_null_fn,
-};
-
-Altera_desc cyclone2 = {
-       Altera_CYC2,
-       passive_serial,
-       Altera_EP2C20_SIZE,
-       (void *) &altera_fns,
-       NULL,
-       0
-};
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int mvblm7_init_fpga(void)
-{
-       fpga_debug("Initialize FPGA interface\n");
-       fpga_init();
-       fpga_add(fpga_altera, &cyclone2);
-       fpga_config_fn(0, 1, 0);
-       udelay(60);
-
-       return 1;
-}
-
-int fpga_null_fn(int cookie)
-{
-       return 0;
-}
-
-int fpga_config_fn(int assert, int flush, int cookie)
-{
-       volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-       volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
-       u32 dvo = gpio->dat;
-
-       fpga_debug("SET config : %s\n", assert ? "low" : "high");
-       if (assert)
-               dvo |= FPGA_CONFIG;
-       else
-               dvo &= ~FPGA_CONFIG;
-
-       if (flush)
-               gpio->dat = dvo;
-
-       return assert;
-}
-
-int fpga_done_fn(int cookie)
-{
-       volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-       volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
-       int result = 0;
-
-       udelay(10);
-       fpga_debug("CONF_DONE check ... ");
-       if (gpio->dat & FPGA_CONF_DONE)  {
-               fpga_debug("high\n");
-               result = 1;
-       } else
-               fpga_debug("low\n");
-
-       return result;
-}
-
-int fpga_status_fn(int cookie)
-{
-       volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-       volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
-       int result = 0;
-
-       fpga_debug("STATUS check ... ");
-       if (gpio->dat & FPGA_STATUS)  {
-               fpga_debug("high\n");
-               result = 1;
-       } else
-               fpga_debug("low\n");
-
-       return result;
-}
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-       volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-       volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
-       u32 dvo = gpio->dat;
-
-       fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
-       if (assert_clk)
-               dvo |= FPGA_CCLK;
-       else
-               dvo &= ~FPGA_CCLK;
-
-       if (flush)
-               gpio->dat = dvo;
-
-       return assert_clk;
-}
-
-static inline int _write_fpga(u8 val, int dump)
-{
-       volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
-       volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
-       int i;
-       u32 dvo = gpio->dat;
-
-       if (dump)
-               fpga_debug("  %02x -> ", val);
-       for (i = 0; i < 8; i++) {
-               dvo &= ~FPGA_CCLK;
-               gpio->dat = dvo;
-               dvo &= ~FPGA_DIN;
-               if (dump)
-                       fpga_debug("%d ", val&1);
-               if (val & 1)
-                       dvo |= FPGA_DIN;
-               gpio->dat = dvo;
-               dvo |= FPGA_CCLK;
-               gpio->dat = dvo;
-               val >>= 1;
-       }
-       if (dump)
-               fpga_debug("\n");
-
-       return 0;
-}
-
-int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
-{
-       unsigned char *data = (unsigned char *) buf;
-       int i;
-
-       fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
-       for (i = 0; i < len; i++)
-               _write_fpga(data[i], 0);
-       fpga_debug("\n");
-
-       return FPGA_SUCCESS;
-}
diff --git a/board/matrix_vision/mvblm7/fpga.h b/board/matrix_vision/mvblm7/fpga.h
deleted file mode 100644 (file)
index b480c09..0000000
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-extern int mvblm7_init_fpga(void);
-
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_status_fn(int cookie);
-extern int fpga_config_fn(int assert, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
-extern int fpga_null_fn(int cookie);
diff --git a/board/matrix_vision/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c
deleted file mode 100644 (file)
index f3c16a3..0000000
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006.
- *
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <asm/mpc8349_pci.h>
-#include <pci.h>
-#include <spi.h>
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-
-#include "../common/mv_common.h"
-#include "mvblm7.h"
-
-int fixed_sdram(void)
-{
-       volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-       u32 msize = 0;
-       u32 ddr_size;
-       u32 ddr_size_log2;
-       char *s = getenv("ddr_size");
-
-       msize = CONFIG_SYS_DDR_SIZE;
-       if (s) {
-               u32 env_ddr_size = simple_strtoul(s, NULL, 10);
-               if (env_ddr_size == 512)
-                       msize = 512;
-       }
-
-       for (ddr_size = msize << 20, ddr_size_log2 = 0;
-            (ddr_size > 1);
-            ddr_size = ddr_size >> 1, ddr_size_log2++) {
-               if (ddr_size & 1)
-                       return -1;
-       }
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
-       im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
-               LAWAR_SIZE);
-
-       im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
-       im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-       im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-       im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-       im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-       im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-       im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-       im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-       im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-       im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-       im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-       im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
-
-       asm("sync;isync");
-       udelay(600);
-
-       im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
-       asm("sync;isync");
-       udelay(500);
-
-       return msize;
-}
-
-phys_size_t initdram(int board_type)
-{
-       volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-       u32 msize = 0;
-
-       if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-               return -1;
-
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-       msize = fixed_sdram();
-
-       /* return total bus RAM size(bytes) */
-       return msize * 1024 * 1024;
-}
-
-int misc_init_r(void)
-{
-       char *s = getenv("reset_env");
-
-       if (s) {
-               mv_reset_environment();
-       }
-
-       return 0;
-}
-
-int checkboard(void)
-{
-       puts("Board: Matrix Vision mvBlueLYNX-M7\n");
-
-       return 0;
-}
-
-#ifdef CONFIG_HARD_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-       return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-       volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
-       iopd->dat &= ~MVBLM7_MMC_CS;
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-       volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
-
-       iopd->dat |= ~MVBLM7_MMC_CS;
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-       ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-       ft_pci_setup(blob, bd);
-#endif
-}
-
-#endif
diff --git a/board/matrix_vision/mvblm7/mvblm7.h b/board/matrix_vision/mvblm7/mvblm7.h
deleted file mode 100644 (file)
index de9fec7..0000000
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __MVBC_H__
-#define __MVBC_H__
-
-#define MV_GPIO
-
-#define FPGA_CONFIG     0x80000000
-#define FPGA_CCLK       0x40000000
-#define FPGA_DIN        0x20000000
-#define FPGA_STATUS     0x10000000
-#define FPGA_CONF_DONE  0x08000000
-
-#define WD_WDI          0x00400000
-#define WD_TS           0x00200000
-#define MAN_RST         0x00100000
-
-#define MV_GPIO_DAT    (WD_TS)
-#define MV_GPIO_OUT    (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS)
-#define MV_GPIO_ODE    (FPGA_CONFIG|MAN_RST)
-
-#endif
diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c
deleted file mode 100644 (file)
index f14837a..0000000
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006.
- *
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-#include <pci.h>
-#include <mpc83xx.h>
-#include <fpga.h>
-#include "mvblm7.h"
-#include "fpga.h"
-#include "../common/mv_common.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pci_region pci_regions[] = {
-       {
-               bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-               phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-               size: CONFIG_SYS_PCI1_MEM_SIZE,
-               flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-       },
-       {
-               bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-               phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-               size: CONFIG_SYS_PCI1_MMIO_SIZE,
-               flags: PCI_REGION_MEM
-       },
-       {
-               bus_start: CONFIG_SYS_PCI1_IO_BASE,
-               phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-               size: CONFIG_SYS_PCI1_IO_SIZE,
-               flags: PCI_REGION_IO
-       }
-};
-
-void pci_init_board(void)
-{
-       int i;
-       volatile immap_t *immr;
-       volatile pcictrl83xx_t *pci_ctrl;
-       volatile gpio83xx_t *gpio;
-       volatile clk83xx_t *clk;
-       volatile law83xx_t *pci_law;
-       struct pci_region *reg[] = { pci_regions };
-
-       immr = (immap_t *) CONFIG_SYS_IMMR;
-       clk = (clk83xx_t *) &immr->clk;
-       pci_ctrl = immr->pci_ctrl;
-       pci_law = immr->sysconf.pcilaw;
-       gpio  = (volatile gpio83xx_t *)&immr->gpio[0];
-
-       gpio->dat = MV_GPIO_DAT;
-       gpio->odr = MV_GPIO_ODE;
-       gpio->dir = MV_GPIO_OUT;
-
-       printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
-               immr->sysconf.sicrl);
-
-       mvblm7_init_fpga();
-       mv_load_fpga();
-
-       gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
-
-       /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
-       clk->occr = 0xc0000000;
-
-       pci_ctrl[0].gcr = 0;
-       udelay(2000);
-       pci_ctrl[0].gcr = 1;
-
-       for (i = 0; i < 1000; ++i)
-               udelay(1000);
-
-       pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-       pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
-
-       pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-       pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-       mpc83xx_pci_init(1, reg);
-}
diff --git a/configs/MERGERBOX_defconfig b/configs/MERGERBOX_defconfig
deleted file mode 100644 (file)
index 34a527e..0000000
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MERGERBOX=y
diff --git a/configs/MVBLM7_defconfig b/configs/MVBLM7_defconfig
deleted file mode 100644 (file)
index cc81b5c..0000000
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MVBLM7=y
index 036bc83..3caa8cf 100644 (file)
@@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+MERGERBOX        powerpc     mpc83xx        -           -           Andre Schwarz <andre.schwarz@matrix-vision.de>
+MVBLM7           powerpc     mpc83xx        -           -           Andre Schwarz <andre.schwarz@matrix-vision.de>
 bluestone        powerpc     ppc4xx         -           -           Tirumala Marri <tmarri@apm.com>
 CRAYL1           powerpc     ppc4xx         -           -           David Updegraff <dave@cray.com>
 KAREF            powerpc     ppc4xx         -           -           Travis Sawyer <travis.sawyer@sandburst.com>
diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h
deleted file mode 100644 (file)
index 19ea316..0000000
+++ /dev/null
@@ -1,599 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2011 Matrix Vision GmbH
- * Andre Schwarz <andre.schwarz@matrix-vision.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300    1
-#define CONFIG_MPC837x 1
-#define CONFIG_MPC8377 1
-
-#define CONFIG_SYS_TEXT_BASE   0xFC000000
-
-#define CONFIG_PCI     1
-#define CONFIG_PCI_INDIRECT_BRIDGE 1
-
-#define        CONFIG_MASK_AER_AO
-#define CONFIG_DISPLAY_AER_FULL
-
-#define CONFIG_MISC_INIT_R
-
-/*
- * On-board devices
- */
-#define CONFIG_TSEC_ENET
-
-/*
- * System Clock Setup
- */
-#define CONFIG_83XX_CLKIN      66666667 /* in Hz */
-#define CONFIG_PCIE
-#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
-#define CONFIG_SYS_CLK_FREQ    CONFIG_83XX_CLKIN
-
-/*
- * Hardware Reset Configuration Word stored in EEPROM.
- */
-#define CONFIG_SYS_HRCW_LOW    0
-#define CONFIG_SYS_HRCW_HIGH   0
-
-/* Arbiter Configuration Register */
-#define CONFIG_SYS_ACR_PIPE_DEP        3
-#define CONFIG_SYS_ACR_RPTCNT  3
-
-/* System Priority Control Regsiter */
-#define CONFIG_SYS_SPCR_TSECEP 3
-
-/* System Clock Configuration Register */
-#define CONFIG_SYS_SCCR_TSEC1CM                3
-#define CONFIG_SYS_SCCR_TSEC2CM                0
-#define CONFIG_SYS_SCCR_SDHCCM         3
-#define CONFIG_SYS_SCCR_ENCCM          3 /* also clock for I2C-1 */
-#define CONFIG_SYS_SCCR_USBDRCM                CONFIG_SYS_SCCR_ENCCM /* must match */
-#define CONFIG_SYS_SCCR_PCIEXP1CM      3
-#define CONFIG_SYS_SCCR_PCIEXP2CM      3
-#define CONFIG_SYS_SCCR_PCICM          1
-#define CONFIG_SYS_SCCR_SATACM         0xFF
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH       0x087c0000
-#define CONFIG_SYS_SICRL       0x40000000
-
-/*
- * Output Buffer Impedance
- */
-#define CONFIG_SYS_OBIR                0x30000000
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR                0xE0000000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_BASE            0x00000000
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_83XX_DDR_USES_CS0
-
-#define CONFIG_SYS_DDRCDR_VALUE                (DDRCDR_EN | DDRCDR_PZ_HIZ |\
-                                        DDRCDR_NZ_HIZ | DDRCDR_ODT |\
-                                        DDRCDR_Q_DRN)
-
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-
-#define CONFIG_SYS_DDR_MODE_WEAK
-#define CONFIG_SYS_DDR_WRITE_DATA_DELAY        2
-#define CONFIG_SYS_DDR_CPO     0x1f
-
-/* SPD table located at offset 0x20 in extended adressing ROM
- * used for HRCW fetch after power-on reset
- */
-#define        CONFIG_SPD_EEPROM
-#define        SPD_EEPROM_ADDRESS      0x50
-#define        SPD_EEPROM_OFFSET       0x20
-#define        SPD_EEPROM_ADDR_LEN     2
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN         (512*1024)
-#define CONFIG_SYS_MALLOC_LEN          (512*1024)
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK       1
-#define CONFIG_SYS_INIT_RAM_ADDR       0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE       0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE -\
-                                        GENERATED_GBL_DATA_SIZE)
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP   LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-#define CONFIG_FSL_ELBC                1
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_WIDTH     FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FLASH_SIZE          64
-
-#define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM     (LBLAWAR_EN | LBLAWAR_64MB)
-
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\
-                                BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR0_PRELIM  (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\
-                                OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\
-                                OR_GPCM_XACS | OR_GPCM_SCY_15 |\
-                                OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\
-                                OR_GPCM_EAD)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS     1
-#define CONFIG_SYS_MAX_FLASH_SECT      512
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT    120000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500 /* Flash Write Timeout (ms) */
-
-/*
- * NAND Flash on the Local Bus
- */
-#define CONFIG_MTD_NAND_VERIFY_WRITE   1
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_NAND_FSL_ELBC           1
-
-#define CONFIG_SYS_NAND_BASE   0xE0600000
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\
-                                BR_PS_8 | BR_MS_FCM | BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\
-                                OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\
-                                OR_FCM_TRLX | OR_FCM_EHTR)
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM     (LBLAWAR_EN | LBLAWAR_32KB)
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX      1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE    1
-#define CONFIG_SYS_NS16550_CLK         get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
-       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
-
-#define CONFIG_CONSOLE         ttyS0
-#define CONFIG_BAUDRATE                115200
-
-/* SERDES */
-#define CONFIG_FSL_SERDES
-#define CONFIG_FSL_SERDES1     0xe3000
-#define CONFIG_FSL_SERDES2     0xe3100
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT       1
-#define CONFIG_OF_BOARD_SETUP  1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED       400000
-#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET      0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED      400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE      0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET     0x3100
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI_MEM_BASE                0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS                CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE                (256 << 20)
-#define CONFIG_SYS_PCI_MMIO_BASE       0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS       CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE       (256 << 20)
-#define CONFIG_SYS_PCI_IO_BASE         0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS         0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE         (1 << 20)
-
-#ifdef CONFIG_PCIE
-#define CONFIG_SYS_PCIE1_BASE          0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_BASE      0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE      (128 << 20)
-#define CONFIG_SYS_PCIE1_MEM_BASE      0xA8000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0xA8000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE      (256 << 20)
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xB8000000
-#define CONFIG_SYS_PCIE1_IO_SIZE       (8 << 20)
-
-#define CONFIG_SYS_PCIE2_BASE          0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_BASE      0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_SIZE      (128 << 20)
-#define CONFIG_SYS_PCIE2_MEM_BASE      0xC8000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      0xC8000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE      (256 << 20)
-#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xD8000000
-#define CONFIG_SYS_PCIE2_IO_SIZE       (8 << 20)
-#endif
-
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
-
-/*
- * TSEC
- */
-#define CONFIG_GMII                    /* MII PHY management */
-#define CONFIG_SYS_VSC8601_SKEWFIX
-#define        CONFIG_SYS_VSC8601_SKEW_TX      3
-#define        CONFIG_SYS_VSC8601_SKEW_RX      3
-
-#define CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME              "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET                0x24000
-#define TSEC1_PHY_ADDR                 0x10
-#define TSEC1_FLAGS                    (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC1_PHYIDX                   0
-
-#define CONFIG_ETHPRIME                        "TSEC0"
-#define CONFIG_HAS_ETH0
-
-/*
- * SATA
- */
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-
-#define CONFIG_SYS_SATA_MAX_DEVICE     2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1_OFFSET        0x18000
-#define CONFIG_SYS_SATA1       (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2_OFFSET        0x19000
-#define CONFIG_SYS_SATA2       (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_LIB_RAND
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_SATA
-
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_JFFS2
-
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND"
-#define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)"
-
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE     1
-
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_LOAD_ADDR   0x2000000
-#define CONFIG_LOADADDR                0x4000000
-#define CONFIG_SYS_CBSIZE      256
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS     16
-#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE
-
-#define CONFIG_LOADS_ECHO              1
-#define CONFIG_SYS_LOADS_BAUD_CHANGE   1
-
-#define CONFIG_SYS_MEMTEST_START       (60<<20)
-#define CONFIG_SYS_MEMTEST_END         (70<<20)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ   (256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
-                                HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2                HID2_HBE
-
-/*
- * MMU Setup
- */
-#define CONFIG_HIGH_BATS       1
-
-/* DDR: cache cacheable */
-#define CONFIG_SYS_SDRAM       CONFIG_SYS_SDRAM_BASE
-
-#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM | BATL_PP_RW |\
-                                BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\
-                                BATU_VP)
-#define CONFIG_SYS_DBAT0L      CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U      CONFIG_SYS_IBAT0U
-
-/* unused */
-#define CONFIG_SYS_IBAT1L      (0)
-#define CONFIG_SYS_IBAT1U      (0)
-#define CONFIG_SYS_DBAT1L      CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U      CONFIG_SYS_IBAT1U
-
-/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L      (CONFIG_SYS_IMMR | BATL_PP_RW |\
-                                BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U      (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\
-                                BATU_VP)
-#define CONFIG_SYS_DBAT2L      CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U      CONFIG_SYS_IBAT2U
-
-/* unused */
-#define CONFIG_SYS_IBAT3L      (0)
-#define CONFIG_SYS_IBAT3U      (0)
-#define CONFIG_SYS_DBAT3L      CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U      CONFIG_SYS_IBAT3U
-
-/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT4L      (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\
-                                BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT4U      (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\
-                                BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L      (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
-                                BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U      CONFIG_SYS_IBAT4U
-
-/* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
-#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\
-                                BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L      CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U      CONFIG_SYS_IBAT5U
-
-/* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L      (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\
-                                BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U      (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\
-                                BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L      CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U      CONFIG_SYS_IBAT6U
-
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L      (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \
-                                BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U      (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\
-                                BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT7L      CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U      CONFIG_SYS_IBAT7U
-
-/*
- * I2C EEPROM settings
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR             0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         2
-#define CONFIG_SYS_EEPROM_SIZE                 0x4000
-
-/*
- * Environment Configuration
- */
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR                0xFFD00000
-#define CONFIG_ENV_SECT_SIZE   0x20000
-#define CONFIG_ENV_SIZE                CONFIG_ENV_SECT_SIZE
-
-/*
- * Video
- */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_SM501_PCI
-#define VIDEO_FB_LITTLE_ENDIAN
-#define CONFIG_CMD_BMP
-#define CONFIG_VIDEO_SM501
-#define CONFIG_VIDEO_SM501_32BPP
-#define CONFIG_VIDEO_SM501_FBMEM_OFFSET        0x10000
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
-
-/*
- * SPI
- */
-#define CONFIG_MPC8XXX_SPI
-
-/*
- * USB
- */
-#define CONFIG_SYS_USB_HOST
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_KEYBOARD
-/*
- *
- */
-#define CONFIG_BOOTDELAY       5
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR       "s"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY  1000
-
-#define MV_CI          "MergerBox"
-#define MV_VCI         "MergerBox"
-#define MV_FPGA_DATA   0xfc100000
-#define MV_FPGA_SIZE   0x00200000
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM     0x02800000
-#define MV_DTB_ADDR_RAM                0x00600000
-#define MV_INITRD_ADDR_RAM     0x01000000
-#define MV_FITADDR             0xfc300000
-#define        MV_SPLAH_ADDR           0xffe00000
-
-#define CONFIG_BOOTCOMMAND     "run i2c_init;if test ${boot_sqfs} -eq 1;"\
-                               "then; run fitboot;else;run ubiboot;fi;"
-#define CONFIG_BOOTARGS                "console=ttyS0,115200n8"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-       "console_nr=0\0"\
-       "stdin=serial\0"\
-       "stdout=serial\0"\
-       "stderr=serial\0"\
-       "boot_sqfs=1\0"\
-       "usb_dr_mode=host\0"\
-       "bootfile=MergerBox.fit\0"\
-       "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\
-       "fpga=0\0"\
-       "fpgadata=" __stringify(MV_FPGA_DATA) "\0"\
-       "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\
-       "mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\
-       "mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\
-       "mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\
-       "uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\
-       "fitaddr=" __stringify(MV_FITADDR) "\0"\
-       "mv_version=" U_BOOT_VERSION "\0"\
-       "mtdids=" MTDIDS_DEFAULT "\0"\
-       "mtdparts=" MTDPARTS_DEFAULT "\0"\
-       "dhcp_client_id=" MV_CI "\0"\
-       "dhcp_vendor-class-identifier=" MV_VCI "\0"\
-       "upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\
-               "protect off all;erase $uboota +0xC0000;"\
-               "cp.b $loadaddr $uboota $filesize\0"\
-       "upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\
-               "cp.b $loadaddr $fpgadata $filesize\0"\
-       "upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\
-               "cp.b $loadaddr $fitaddr $filesize\0"\
-       "addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\
-               "rootfstype=squashfs\0"\
-       "addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\
-               "rootfstype=ubifs\0"\
-       "addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\
-               "rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\
-       "netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\
-       "netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\
-       "ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\
-       "doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\
-       "fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\
-               "imxtract $fitaddr ramdisk $mv_initrd_ram;"\
-               "imxtract $fitaddr fdt $mv_dtb_ram\0"\
-       "fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\
-       "fitboot=run fitprep fdtprep addsqshrfs doboot\0"\
-       "i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\
-       "i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\
-               "i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\
-               "i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\
-       "i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\
-       "init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\
-               "i2c mw 21 2 ff;i2c mw 21 3 3c\0"\
-       "splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\
-       ""
-
-/*
- * FPGA
- */
-#define CONFIG_FPGA_COUNT      1
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_CYCLON2
-
-#endif
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
deleted file mode 100644 (file)
index 1ee4d7c..0000000
+++ /dev/null
@@ -1,491 +0,0 @@
-/*
- * Copyright (C) Matrix Vision GmbH 2008
- *
- * Matrix Vision mvBlueLYNX-M7 configuration file
- * based on Freescale's MPC8349ITX.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300    1
-#define CONFIG_MPC834x 1
-#define CONFIG_MPC8343 1
-
-#define        CONFIG_SYS_TEXT_BASE    0xFFF00000
-
-#define CONFIG_SYS_IMMR                0xE0000000
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_SKIP_HOST_BRIDGE
-#define CONFIG_TSEC_ENET
-#define CONFIG_MPC8XXX_SPI
-#define CONFIG_HARD_SPI
-#define MVBLM7_MMC_CS   0x04000000
-#define CONFIG_MISC_INIT_R
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED       100000
-#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET      0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED      100000
-#define CONFIG_SYS_FSL_I2C2_SLAVE      0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET     0x3100
-
-/*
- * DDR Setup
- */
-#undef CONFIG_SPD_EEPROM
-
-#define CONFIG_SYS_DDR_BASE            0x00000000
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_83XX_DDR_USES_CS0   1
-#define CONFIG_SYS_MEMTEST_START       (60<<20)
-#define CONFIG_SYS_MEMTEST_END         (70<<20)
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_SYS_DDRCDR              (DDRCDR_PZ_HIZ \
-                                       | DDRCDR_NZ_HIZ \
-                                       | DDRCDR_Q_DRN)
-                                       /* 0x22000001 */
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-
-#define CONFIG_SYS_DDR_SIZE            512
-
-#define CONFIG_SYS_DDR_CS0_CONFIG      0x80014202
-
-#define CONFIG_SYS_DDR_CS0_BNDS                0x0000003f
-
-#define CONFIG_SYS_DDR_TIMING_0                0x00260802
-#define CONFIG_SYS_DDR_TIMING_1                0x3837c322
-#define CONFIG_SYS_DDR_TIMING_2                0x0f9848c6
-#define CONFIG_SYS_DDR_TIMING_3                0x00000000
-
-#define CONFIG_SYS_DDR_SDRAM_CFG       0x43080008
-#define CONFIG_SYS_DDR_SDRAM_CFG2      0x00401000
-#define CONFIG_SYS_DDR_INTERVAL                0x02000100
-
-#define CONFIG_SYS_DDR_MODE            0x04040242
-#define CONFIG_SYS_DDR_MODE2           0x00800000
-
-/* Flash */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_WIDTH     FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_BASE          0xFF800000
-#define CONFIG_SYS_FLASH_SIZE          8
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500
-#define CONFIG_SYS_MAX_FLASH_BANKS     1
-#define CONFIG_SYS_MAX_FLASH_SECT      256
-
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16 \
-                               | BR_MS_GPCM \
-                               | BR_V)
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-                               | OR_UPM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-#define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM     (LBLAWAR_EN | LBLAWAR_8MB)
-
-/*
- * U-Boot memory configuration
- */
-#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE
-#undef CONFIG_SYS_RAMBOOT
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR       0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE       0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET     \
-                       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN          (512 * 1024)
-
-/*
- * Local Bus LCRR and LBCR regs
- *  LCRR:  DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *  CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP   LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
-/* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT    0x32000000
-/* LB refresh timer prescal, 266MHz/32*/
-#define CONFIG_SYS_LBC_MRTPR   0x20000000
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX      1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE    1
-#define CONFIG_SYS_NS16550_CLK         get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-               {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_CONSOLE         ttyS0
-#define CONFIG_BAUDRATE                115200
-
-#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR + 0x4600)
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT               1
-#define CONFIG_OF_BOARD_SETUP          1
-#define CONFIG_OF_STDOUT_VIA_ALIAS     1
-#define MV_DTB_NAME    "mvblm7.dtb"
-
-/*
- * PCI
- */
-#define CONFIG_SYS_PCI1_MEM_BASE       0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE       0x10000000
-#define CONFIG_SYS_PCI1_MMIO_BASE      \
-                       (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI1_MMIO_PHYS      CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE      0x10000000
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS        0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE        0x01000000
-
-#define CONFIG_NET_RETRY_COUNT 3
-
-#define CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN      66666667
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-
-/* TSEC */
-#define CONFIG_GMII
-#define CONFIG_SYS_VSC8601_SKEWFIX
-#define        CONFIG_SYS_VSC8601_SKEW_TX      3
-#define        CONFIG_SYS_VSC8601_SKEW_RX      3
-
-#define CONFIG_TSEC1
-#define CONFIG_TSEC2
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME      "TSEC0"
-#define CONFIG_FEC1_PHY_NORXERR
-#define CONFIG_SYS_TSEC1_OFFSET        0x24000
-#define CONFIG_SYS_TSEC1       (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define TSEC1_PHY_ADDR         0x10
-#define TSEC1_PHYIDX           0
-#define TSEC1_FLAGS            (TSEC_GIGABIT|TSEC_REDUCED)
-
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME      "TSEC1"
-#define CONFIG_FEC2_PHY_NORXERR
-#define CONFIG_SYS_TSEC2_OFFSET        0x25000
-#define CONFIG_SYS_TSEC2       (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-#define TSEC2_PHY_ADDR         0x11
-#define TSEC2_PHYIDX           0
-#define TSEC2_FLAGS            (TSEC_GIGABIT|TSEC_REDUCED)
-
-#define CONFIG_ETHPRIME                "TSEC0"
-
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_LIB_RAND
-
-/* USB */
-#define CONFIG_SYS_USB_HOST
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-/*
- * Environment
- */
-#undef  CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR                0xFF800000
-#define CONFIG_ENV_SIZE                0x2000
-#define CONFIG_ENV_SECT_SIZE   0x2000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-#define CONFIG_LOADS_ECHO
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_USB
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_WATCHDOG
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE   /* add autocompletion support   */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR   0x2000000
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR        0x200000
-
-#define CONFIG_SYS_PROMPT      "mvBL-M7> "
-#define CONFIG_SYS_CBSIZE      256
-
-#define CONFIG_SYS_PBSIZE      \
-                       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS     16
-#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-                               /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ   (256 << 20)
-
-#define CONFIG_SYS_HRCW_LOW    0x0
-#define CONFIG_SYS_HRCW_HIGH   0x0
-
-/*
- * System performance
- */
-#define CONFIG_SYS_ACR_PIPE_DEP        3       /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT  3       /* Arbiter repeat count (0-7) */
-#define CONFIG_SYS_SPCR_TSEC1EP        3       /* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP        3       /* TSEC2 emergency priority (0-3) */
-
-/* clocking */
-#define CONFIG_SYS_SCCR_ENCCM          0
-#define CONFIG_SYS_SCCR_USBMPHCM       0
-#define        CONFIG_SYS_SCCR_USBDRCM 2
-#define CONFIG_SYS_SCCR_TSEC1CM        1
-#define CONFIG_SYS_SCCR_TSEC2CM        1
-
-#define CONFIG_SYS_SICRH       0x1fef0003
-#define CONFIG_SYS_SICRL       (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
-
-#define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (CONFIG_SYS_HID0_INIT | \
-                                HID0_ENABLE_INSTRUCTION_CACHE)
-
-#define CONFIG_SYS_HID2        HID2_HBE
-#define CONFIG_HIGH_BATS       1
-
-/* DDR  */
-#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE \
-                               | BATL_PP_RW \
-                               | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM_BASE \
-                               | BATU_BL_256M \
-                               | BATU_VS \
-                               | BATU_VP)
-
-/* PCI  */
-#define CONFIG_SYS_IBAT1L      (CONFIG_SYS_PCI1_MEM_BASE \
-                               | BATL_PP_RW \
-                               | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U      (CONFIG_SYS_PCI1_MEM_BASE \
-                               | BATU_BL_256M \
-                               | BATU_VS \
-                               | BATU_VP)
-#define CONFIG_SYS_IBAT2L      (CONFIG_SYS_PCI1_MMIO_BASE \
-                               | BATL_PP_RW \
-                               | BATL_CACHEINHIBIT \
-                               | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U      (CONFIG_SYS_PCI1_MMIO_BASE \
-                               | BATU_BL_256M \
-                               | BATU_VS \
-                               | BATU_VP)
-
-/* no PCI2 */
-#define CONFIG_SYS_IBAT3L      0
-#define CONFIG_SYS_IBAT3U      0
-#define CONFIG_SYS_IBAT4L      0
-#define CONFIG_SYS_IBAT4U      0
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_IMMR \
-                               | BATL_PP_RW \
-                               | BATL_CACHEINHIBIT \
-                               | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_IMMR \
-                               | BATU_BL_256M \
-                               | BATU_VS \
-                               | BATU_VP)
-
-/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
-#define CONFIG_SYS_IBAT6L      (0xF0000000 \
-                               | BATL_PP_RW \
-                               | BATL_MEMCOHERENCE \
-                               | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U      (0xF0000000 \
-                               | BATU_BL_256M \
-                               | BATU_VS \
-                               | BATU_VP)
-#define CONFIG_SYS_IBAT7L      0
-#define CONFIG_SYS_IBAT7U      0
-
-#define CONFIG_SYS_DBAT0L      CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U      CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L      CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U      CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L      CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U      CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L      CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U      CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L      CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U      CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L      CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U      CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L      CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U      CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L      CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U      CONFIG_SYS_IBAT7U
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_NETDEV          eth0
-
-/* Default path and filenames */
-#define CONFIG_BOOTDELAY               5
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR       "s"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY          1000
-
-#define MV_CI                  "mvBL-M7"
-#define MV_VCI                 "mvBL-M7"
-#define MV_FPGA_DATA           0xfff40000
-#define MV_FPGA_SIZE           0
-#define MV_KERNEL_ADDR         0xff810000
-#define MV_INITRD_ADDR         0xffb00000
-#define MV_SCRIPT_ADDR         0xff804000
-#define MV_SCRIPT_ADDR2                0xff806000
-#define MV_DTB_ADDR            0xff808000
-#define MV_INITRD_LENGTH       0x00400000
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM     0x00100000
-#define MV_DTB_ADDR_RAM                0x00600000
-#define MV_INITRD_ADDR_RAM     0x01000000
-
-#define CONFIG_BOOTCOMMAND     "if imi ${script_addr}; "               \
-                                       "then source ${script_addr}; "  \
-                                       "else source ${script_addr2}; " \
-                               "fi;"
-#define CONFIG_BOOTARGS                "root=/dev/ram ro rootfstype=squashfs"
-
-#define CONFIG_EXTRA_ENV_SETTINGS                              \
-       "console_nr=0\0"                                        \
-       "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"           \
-       "stdin=serial\0"                                        \
-       "stdout=serial\0"                                       \
-       "stderr=serial\0"                                       \
-       "fpga=0\0"                                              \
-       "fpgadata=" __stringify(MV_FPGA_DATA) "\0"                      \
-       "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"          \
-       "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"         \
-       "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0"               \
-       "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"              \
-       "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"      \
-       "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"              \
-       "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"      \
-       "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"  \
-       "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0"                    \
-       "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"            \
-       "dtb_name=" __stringify(MV_DTB_NAME) "\0"                       \
-       "mv_version=" U_BOOT_VERSION "\0"                       \
-       "dhcp_client_id=" MV_CI "\0"                            \
-       "dhcp_vendor-class-identifier=" MV_VCI "\0"             \
-       "netretry=no\0"                                         \
-       "use_static_ipaddr=no\0"                                \
-       "static_ipaddr=192.168.90.10\0"                         \
-       "static_netmask=255.255.255.0\0"                        \
-       "static_gateway=0.0.0.0\0"                              \
-       "initrd_name=uInitrd.mvBL-M7-rfs\0"                     \
-       "zcip=no\0"                                             \
-       "netboot=yes\0"                                         \
-       "mvtest=Ff\0"                                           \
-       "tried_bootfromflash=no\0"                              \
-       "tried_bootfromnet=no\0"                                \
-       "bootfile=mvblm72625.boot\0"                            \
-       "use_dhcp=yes\0"                                        \
-       "gev_start=yes\0"                                       \
-       "mvbcdma_debug=0\0"                                     \
-       "mvbcia_debug=0\0"                                      \
-       "propdev_debug=0\0"                                     \
-       "gevss_debug=0\0"                                       \
-       "watchdog=0\0"                                          \
-       "usb_dr_mode=host\0"                                    \
-       "sensor_cnt=2\0"                                        \
-       ""
-
-#define CONFIG_FPGA_COUNT      1
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_CYCLON2
-
-#endif