ARM: dts: stm32: add pinctrl sleep config for qspi on stm32mp157c-ev1

This patch adds pinctrl sleep config for qspi on stm32mp157c-ev1

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>

diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index 60453d5..f6996b4 100644 (file)
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -481,6 +481,12 @@
                                };
                        };
 
+                       qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
+                               };
+                       };
+
                        qspi_bk1_pins_a: qspi-bk1-0 {
                                pins1 {
                                        pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
@@ -499,6 +505,16 @@
                                };
                        };
 
+                       qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
+                                                <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
+                                                <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
+                                                <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
+                                                <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
+                               };
+                       };
+
                        qspi_bk2_pins_a: qspi-bk2-0 {
                                pins1 {
                                        pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
@@ -517,6 +533,16 @@
                                };
                        };
 
+                       qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
+                                                <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
+                                                <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
+                                                <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
+                                                <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
+                               };
+                       };
+
                        sdmmc1_b4_pins_a: sdmmc1-b4-0 {
                                pins {
                                        pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */

diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index 01438ac..0f2f8be 100644 (file)
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -192,8 +192,9 @@
 };
 
 &qspi {
-       pinctrl-names = "default";
+       pinctrl-names = "default", "sleep";
        pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
+       pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
        reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
        #address-cells = <1>;
        #size-cells = <0>;