MIPS patches 2015-10-30
Changes:
* R6 CPU can be woken up by non-enabled interrupts
* PC fix in KVM
* Coprocessor 0 XContext calculation fix
* various MIPS R6 updates
# gpg: Signature made Fri 30 Oct 2015 14:51:56 GMT using RSA key ID
0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
* remotes/lalrae/tags/mips-
20151030:
target-mips: fix updating XContext on mmu exception
target-mips: add SIGRIE instruction
target-mips: Set Config5.XNP for R6 cores
target-mips: add PC, XNP reg numbers to RDHWR
hw/mips_malta: Fix KVM PC initialisation
target-mips: Add enum for BREAK32
target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6
target-mips: implement the CPU wake-up on non-enabled interrupts in R6
target-mips: move the test for enabled interrupts to a separate function
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>