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RDMA/hns: Fix query destination qpn
author
Wenpeng Liang
<liangwenpeng@huawei.com>
Thu, 26 Aug 2021 13:37:30 +0000
(21:37 +0800)
committer
Jason Gunthorpe
<jgg@nvidia.com>
Thu, 26 Aug 2021 15:12:20 +0000
(12:12 -0300)
The bit width of dqpn is 24 bits, using u8 will cause truncation error.
Fixes: 926a01dc000d ("RDMA/hns: Add QP operations support for hip08 SoC")
Link:
https://lore.kernel.org/r/1629985056-57004-2-git-send-email-liangwenpeng@huawei.com
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
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diff --git
a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index 50a6f918cf1c43024cdca672bdc7645a1d246aae..752bad5d5f8095620c6f3c5ae81a2f4ba51d5c07 100644
(file)
--- a/
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@
-5130,7
+5130,7
@@
static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN);
qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN);
- qp_attr->dest_qp_num =
(u8)
hr_reg_read(&context, QPC_DQPN);
+ qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN);
qp_attr->qp_access_flags =
((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) |
((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) |