arm64: dts: juno: add CTI entries to device tree

Add Coresight Cross Trigger Interface(CTI) entries to the device tree
for all the Juno variants.

Link: https://lore.kernel.org/r/20220413214925.30359-1-mike.leach@linaro.org
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 446c8f4..4f40a5c 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -117,7 +117,7 @@
         * The actual size is just 4K though 64K is reserved. Access to the
         * unmapped reserved region results in a DECERR response.
         */
-       etf@20010000 { /* etf0 */
+       etf_sys0: etf@20010000 { /* etf0 */
                compatible = "arm,coresight-tmc", "arm,primecell";
                reg = <0 0x20010000 0 0x1000>;
 
@@ -141,7 +141,7 @@
                };
        };
 
-       tpiu@20030000 {
+       tpiu_sys: tpiu@20030000 {
                compatible = "arm,coresight-tpiu", "arm,primecell";
                reg = <0 0x20030000 0 0x1000>;
 
@@ -194,7 +194,7 @@
                };
        };
 
-       etr@20070000 {
+       etr_sys: etr@20070000 {
                compatible = "arm,coresight-tmc", "arm,primecell";
                reg = <0 0x20070000 0 0x1000>;
                iommus = <&smmu_etr 0>;
@@ -212,7 +212,7 @@
                };
        };
 
-       stm@20100000 {
+       stm_sys: stm@20100000 {
                compatible = "arm,coresight-stm", "arm,primecell";
                reg = <0 0x20100000 0 0x1000>,
                      <0 0x28000000 0 0x1000000>;
@@ -289,6 +289,18 @@
                };
        };
 
+       cti0: cti@22020000 {
+               compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+                            "arm,primecell";
+               reg = <0 0x22020000 0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+
+               arm,cs-dev-assoc = <&etm0>;
+       };
+
        funnel@220c0000 { /* cluster0 funnel */
                compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
                reg = <0 0x220c0000 0 0x1000>;
@@ -349,6 +361,18 @@
                };
        };
 
+       cti1: cti@22120000 {
+               compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+                            "arm,primecell";
+               reg = <0 0x22120000 0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+
+               arm,cs-dev-assoc = <&etm1>;
+       };
+
        cpu_debug2: cpu-debug@23010000 {
                compatible = "arm,coresight-cpu-debug", "arm,primecell";
                reg = <0x0 0x23010000 0x0 0x1000>;
@@ -374,6 +398,18 @@
                };
        };
 
+       cti2: cti@23020000 {
+               compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+                            "arm,primecell";
+               reg = <0 0x23020000 0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+
+               arm,cs-dev-assoc = <&etm2>;
+       };
+
        funnel@230c0000 { /* cluster1 funnel */
                compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
                reg = <0 0x230c0000 0 0x1000>;
@@ -446,6 +482,18 @@
                };
        };
 
+       cti3: cti@23120000 {
+               compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+                            "arm,primecell";
+               reg = <0 0x23120000 0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+
+               arm,cs-dev-assoc = <&etm3>;
+       };
+
        cpu_debug4: cpu-debug@23210000 {
                compatible = "arm,coresight-cpu-debug", "arm,primecell";
                reg = <0x0 0x23210000 0x0 0x1000>;
@@ -471,6 +519,18 @@
                };
        };
 
+       cti4: cti@23220000 {
+               compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+                            "arm,primecell";
+               reg = <0 0x23220000 0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+
+               arm,cs-dev-assoc = <&etm4>;
+       };
+
        cpu_debug5: cpu-debug@23310000 {
                compatible = "arm,coresight-cpu-debug", "arm,primecell";
                reg = <0x0 0x23310000 0x0 0x1000>;
@@ -496,6 +556,100 @@
                };
        };
 
+       cti5: cti@23320000 {
+               compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
+                            "arm,primecell";
+               reg = <0 0x23320000 0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+
+               arm,cs-dev-assoc = <&etm5>;
+       };
+
+       cti_sys0: cti@20020000 { /* sys_cti_0 */
+               compatible = "arm,coresight-cti", "arm,primecell";
+               reg = <0 0x20020000 0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               trig-conns@0 {
+                       reg = <0>;
+                       arm,trig-in-sigs=<2 3>;
+                       arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>;
+                       arm,trig-out-sigs=<0 1>;
+                       arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
+                       arm,cs-dev-assoc = <&etr_sys>;
+               };
+
+               trig-conns@1 {
+                       reg = <1>;
+                       arm,trig-in-sigs=<0 1>;
+                       arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>;
+                       arm,trig-out-sigs=<7 6>;
+                       arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
+                       arm,cs-dev-assoc = <&etf_sys0>;
+               };
+
+               trig-conns@2 {
+                       reg = <2>;
+                       arm,trig-in-sigs=<4 5 6 7>;
+                       arm,trig-in-types=<STM_TOUT_SPTE STM_TOUT_SW
+                                          STM_TOUT_HETE STM_ASYNCOUT>;
+                       arm,trig-out-sigs=<4 5>;
+                       arm,trig-out-types=<STM_HWEVENT STM_HWEVENT>;
+                       arm,cs-dev-assoc = <&stm_sys>;
+               };
+
+               trig-conns@3 {
+                       reg = <3>;
+                       arm,trig-out-sigs=<2 3>;
+                       arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
+                       arm,cs-dev-assoc = <&tpiu_sys>;
+               };
+       };
+
+       cti_sys1: cti@20110000 { /* sys_cti_1 */
+               compatible = "arm,coresight-cti", "arm,primecell";
+               reg = <0 0x20110000 0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               trig-conns@0 {
+                       reg = <0>;
+                       arm,trig-in-sigs=<0>;
+                       arm,trig-in-types=<GEN_INTREQ>;
+                       arm,trig-out-sigs=<0>;
+                       arm,trig-out-types=<GEN_HALTREQ>;
+                       arm,trig-conn-name = "sys_profiler";
+               };
+
+               trig-conns@1 {
+                       reg = <1>;
+                       arm,trig-out-sigs=<2 3>;
+                       arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
+                       arm,trig-conn-name = "watchdog";
+               };
+
+               trig-conns@2 {
+                       reg = <2>;
+                       arm,trig-out-sigs=<1 6>;
+                       arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
+                       arm,trig-conn-name = "g_counter";
+               };
+       };
+
        gpu: gpu@2d000000 {
                compatible = "arm,juno-mali", "arm,mali-t624";
                reg = <0 0x2d000000 0 0x10000>;

diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
index eda3d9e..2e43f45 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
@@ -23,7 +23,7 @@
                };
        };
 
-       etf@20140000 { /* etf1 */
+       etf_sys1: etf@20140000 { /* etf1 */
                compatible = "arm,coresight-tmc", "arm,primecell";
                reg = <0 0x20140000 0 0x1000>;
 
@@ -82,4 +82,39 @@
 
                };
        };
+
+       cti_sys2: cti@20160000 { /* sys_cti_2 */
+               compatible = "arm,coresight-cti", "arm,primecell";
+               reg = <0 0x20160000 0 0x1000>;
+
+               clocks = <&soc_smc50mhz>;
+               clock-names = "apb_pclk";
+               power-domains = <&scpi_devpd 0>;
+
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               trig-conns@0 {
+                       reg = <0>;
+                       arm,trig-in-sigs=<0 1>;
+                       arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>;
+                       arm,trig-out-sigs=<0 1>;
+                       arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
+                       arm,cs-dev-assoc = <&etf_sys1>;
+               };
+
+               trig-conns@1 {
+                       reg = <1>;
+                       arm,trig-in-sigs=<2 3 4>;
+                       arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
+                       arm,trig-conn-name = "ela_clus_0";
+               };
+
+               trig-conns@2 {
+                       reg = <2>;
+                       arm,trig-in-sigs=<5 6 7>;
+                       arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
+                       arm,trig-conn-name = "ela_clus_1";
+               };
+       };
 };

diff --git a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts
index fd1f0d2..dd9ea69 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts
@@ -15,6 +15,10 @@
        };
 };
 
+&cti_sys2 {
+       power-domains = <&scmi_devpd 8>;
+};
+
 &A57_0 {
        clocks = <&scmi_dvfs 0>;
 };

diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index 0e24e29..f099fb6 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -9,6 +9,7 @@
 /dts-v1/;
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/arm/coresight-cti-dt.h>
 #include "juno-base.dtsi"
 #include "juno-cs-r1r2.dtsi"
 
@@ -313,3 +314,27 @@
 &cpu_debug5 {
        cpu = <&A53_3>;
 };
+
+&cti0 {
+       cpu = <&A57_0>;
+};
+
+&cti1 {
+       cpu = <&A57_1>;
+};
+
+&cti2 {
+       cpu = <&A53_0>;
+};
+
+&cti3 {
+       cpu = <&A53_1>;
+};
+
+&cti4 {
+       cpu = <&A53_2>;
+};
+
+&cti5 {
+       cpu = <&A53_3>;
+};

diff --git a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts
index 35e6d47..de2cbac 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts
@@ -15,6 +15,10 @@
        };
 };
 
+&cti_sys2 {
+       power-domains = <&scmi_devpd 8>;
+};
+
 &A72_0 {
        clocks = <&scmi_dvfs 0>;
 };

diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
index e609420..7093895 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno-r2.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
@@ -9,6 +9,7 @@
 /dts-v1/;
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/arm/coresight-cti-dt.h>
 #include "juno-base.dtsi"
 #include "juno-cs-r1r2.dtsi"
 
@@ -319,3 +320,27 @@
 &cpu_debug5 {
        cpu = <&A53_3>;
 };
+
+&cti0 {
+       cpu = <&A72_0>;
+};
+
+&cti1 {
+       cpu = <&A72_1>;
+};
+
+&cti2 {
+       cpu = <&A53_0>;
+};
+
+&cti3 {
+       cpu = <&A53_1>;
+};
+
+&cti4 {
+       cpu = <&A53_2>;
+};
+
+&cti5 {
+       cpu = <&A53_3>;
+};

diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dtsi b/arch/arm64/boot/dts/arm/juno-scmi.dtsi
index d72dcff..4135d62 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno-scmi.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-scmi.dtsi
@@ -154,6 +154,31 @@
        power-domains = <&scmi_devpd 8>;
 };
 
+&cti0 {
+       power-domains = <&scmi_devpd 8>;
+};
+&cti1 {
+       power-domains = <&scmi_devpd 8>;
+};
+&cti2 {
+       power-domains = <&scmi_devpd 8>;
+};
+&cti3 {
+       power-domains = <&scmi_devpd 8>;
+};
+&cti4 {
+       power-domains = <&scmi_devpd 8>;
+};
+&cti5 {
+       power-domains = <&scmi_devpd 8>;
+};
+&cti_sys0 {
+       power-domains = <&scmi_devpd 8>;
+};
+&cti_sys1 {
+       power-domains = <&scmi_devpd 8>;
+};
+
 &gpu {
        clocks = <&scmi_dvfs 2>;
        power-domains = <&scmi_devpd 9>;

diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index f00cffb..dbc22e7 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -9,6 +9,7 @@
 /dts-v1/;
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/arm/coresight-cti-dt.h>
 #include "juno-base.dtsi"
 
 / {
@@ -295,3 +296,27 @@
 &cpu_debug5 {
        cpu = <&A53_3>;
 };
+
+&cti0 {
+       cpu = <&A57_0>;
+};
+
+&cti1 {
+       cpu = <&A57_1>;
+};
+
+&cti2 {
+       cpu = <&A53_0>;
+};
+
+&cti3 {
+       cpu = <&A53_1>;
+};
+
+&cti4 {
+       cpu = <&A53_2>;
+};
+
+&cti5 {
+       cpu = <&A53_3>;
+};