{ \
Tvec v0 = ld_func(0, ptr); \
Tvec v1 = ld_func(2, ptr); \
- a = vec_mergeh(v0, v1); \
- b = vec_mergel(v0, v1); \
- v0 = ld_func(4, ptr); \
- v1 = ld_func(6, ptr); \
- c = vec_mergeh(v0, v1); \
- d = vec_mergel(v0, v1); \
+ Tvec v2 = ld_func(4, ptr); \
+ Tvec v3 = ld_func(6, ptr); \
+ a = vec_mergeh(v0, v2); \
+ b = vec_mergel(v0, v2); \
+ c = vec_mergeh(v1, v3); \
+ d = vec_mergel(v1, v3); \
}
-VSX_IMPL_ST_D_INTERLEAVE_64(int64, vec_dword2, vsx_ld2, vsx_st2)
+VSX_IMPL_ST_D_INTERLEAVE_64(int64, vec_dword2, vsx_ld2, vsx_st2)
VSX_IMPL_ST_D_INTERLEAVE_64(uint64, vec_udword2, vsx_ld2, vsx_st2)
-VSX_IMPL_ST_D_INTERLEAVE_64(double, vec_double2, vsx_ld, vsx_st)
+VSX_IMPL_ST_D_INTERLEAVE_64(double, vec_double2, vsx_ld, vsx_st)
/* 3 channels */
#define VSX_IMPL_ST_INTERLEAVE_3CH_16(Tp, Tvec) \