MIPS: DTS: CI20: fix reset line polarity of the ethernet controller

commit ca637c0ece144ce62ec8ef75dc127bcccd4f442a upstream.

The reset line is called PWRST#, annotated as "active low" in the
binding documentation, and is driven low and then high by the driver to
reset the chip. However in device tree for CI20 board it was incorrectly
marked as "active high". Fix it.

Because (as far as I know) the ci20.dts is always built in the kernel I
elected not to also add a quirk to gpiolib to force the polarity there.

Fixes: db49ca38579d ("net: davicom: dm9000: switch to using gpiod API")
Reported-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 37c4672..f38c395 100644 (file)
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -438,7 +438,7 @@
                ingenic,nemc-tAW = <50>;
                ingenic,nemc-tSTRV = <100>;
 
-               reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
+               reset-gpios = <&gpf 12 GPIO_ACTIVE_LOW>;
                vcc-supply = <&eth0_power>;
 
                interrupt-parent = <&gpe>;