[AArch64] Fixes for ARMv8.2-A FP16 scalar intrinsic - llvm portion

https://reviews.llvm.org/D42993

llvm-svn: 324912

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 2b49a7a..eca16bd 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3530,6 +3530,8 @@ def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
           (FCVTPUv1i64 FPR64:$Rn)>;
 
+def : Pat<(f16 (int_aarch64_neon_frecpe (f16 FPR16:$Rn))),
+          (FRECPEv1f16 FPR16:$Rn)>;
 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
           (FRECPEv1i32 FPR32:$Rn)>;
 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
@@ -3561,11 +3563,15 @@ def : Pat<(f64 (AArch64frecps (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
 def : Pat<(v2f64 (AArch64frecps (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))),
           (FRECPSv2f64 FPR128:$Rn, FPR128:$Rm)>;
 
+def : Pat<(f16 (int_aarch64_neon_frecpx (f16 FPR16:$Rn))),
+          (FRECPXv1f16 FPR16:$Rn)>;
 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
           (FRECPXv1i32 FPR32:$Rn)>;
 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
           (FRECPXv1i64 FPR64:$Rn)>;
 
+def : Pat<(f16 (int_aarch64_neon_frsqrte (f16 FPR16:$Rn))),
+          (FRSQRTEv1f16 FPR16:$Rn)>;
 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
           (FRSQRTEv1i32 FPR32:$Rn)>;
 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),

diff --git a/llvm/test/CodeGen/AArch64/f16-instructions.ll b/llvm/test/CodeGen/AArch64/f16-instructions.ll
index 2aade50..c6c279d 100644 (file)
--- a/llvm/test/CodeGen/AArch64/f16-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/f16-instructions.ll
@@ -736,6 +736,9 @@ declare half @llvm.rint.f16(half %a) #0
 declare half @llvm.nearbyint.f16(half %a) #0
 declare half @llvm.round.f16(half %a) #0
 declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #0
+declare half @llvm.aarch64.neon.frecpe.f16(half %a) #0
+declare half @llvm.aarch64.neon.frecpx.f16(half %a) #0
+declare half @llvm.aarch64.neon.frsqrte.f16(half %a) #0
 
 ; CHECK-CVT-LABEL: test_sqrt:
 ; CHECK-CVT-NEXT: fcvt s0, h0
@@ -1124,4 +1127,31 @@ define half @test_fmuladd(half %a, half %b, half %c) #0 {
   ret half %r
 }
 
+; CHECK-FP16-LABEL: test_vrecpeh_f16:
+; CHECK-FP16-NEXT: frecpe h0, h0
+; CHECK-FP16-NEXT: ret
+
+define half @test_vrecpeh_f16(half %a) #0 {
+  %r = call half @llvm.aarch64.neon.frecpe.f16(half %a)
+  ret half %r
+}
+
+; CHECK-FP16-LABEL: test_vrecpxh_f16:
+; CHECK-FP16-NEXT: frecpx h0, h0
+; CHECK-FP16-NEXT: ret
+
+define half @test_vrecpxh_f16(half %a) #0 {
+  %r = call half @llvm.aarch64.neon.frecpx.f16(half %a)
+  ret half %r
+}
+
+; CHECK-FP16-LABEL: test_vrsqrteh_f16:
+; CHECK-FP16-NEXT: frsqrte h0, h0
+; CHECK-FP16-NEXT: ret
+
+define half @test_vrsqrteh_f16(half %a) #0 {
+  %r = call half @llvm.aarch64.neon.frsqrte.f16(half %a)
+  ret half %r
+}
+
 attributes #0 = { nounwind }