[ELF][AArch64] Implement the AArch64 TLSLD_LDST_LO12 family of relocs

Implement the following relocations for AArch64:
R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC

These are specified in ELF for the 64-bit Arm Architecture.

Fixes pr36727

Differential Revision: https://reviews.llvm.org/D46255

llvm-svn: 331511

diff --git a/lld/ELF/Arch/AArch64.cpp b/lld/ELF/Arch/AArch64.cpp
index e2e054e62091a60c8383dc8d6b17be6f3794c856..c7b3c0801de213a9b6ef3ac9580f40c90dca8732 100644 (file)
--- a/lld/ELF/Arch/AArch64.cpp
+++ b/lld/ELF/Arch/AArch64.cpp
@@ -89,6 +89,11 @@ RelExpr AArch64::getRelExpr(RelType Type, const Symbol &S,
     return R_TLSDESC_CALL;
   case R_AARCH64_TLSLE_ADD_TPREL_HI12:
   case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+  case R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
+  case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
+  case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
+  case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
+  case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
     return R_TLS;
   case R_AARCH64_CALL26:
   case R_AARCH64_CONDBR19:
@@ -290,24 +295,29 @@ void AArch64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
     or32le(Loc, (Val & 0x1FFFFC) << 3);
     break;
   case R_AARCH64_LDST8_ABS_LO12_NC:
+  case R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
     or32AArch64Imm(Loc, getBits(Val, 0, 11));
     break;
   case R_AARCH64_LDST16_ABS_LO12_NC:
+  case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
     checkAlignment(Loc, Val, 2, Type);
     or32AArch64Imm(Loc, getBits(Val, 1, 11));
     break;
   case R_AARCH64_LDST32_ABS_LO12_NC:
+  case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
     checkAlignment(Loc, Val, 4, Type);
     or32AArch64Imm(Loc, getBits(Val, 2, 11));
     break;
   case R_AARCH64_LDST64_ABS_LO12_NC:
   case R_AARCH64_LD64_GOT_LO12_NC:
   case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+  case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
   case R_AARCH64_TLSDESC_LD64_LO12:
     checkAlignment(Loc, Val, 8, Type);
     or32AArch64Imm(Loc, getBits(Val, 3, 11));
     break;
   case R_AARCH64_LDST128_ABS_LO12_NC:
+  case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
     checkAlignment(Loc, Val, 16, Type);
     or32AArch64Imm(Loc, getBits(Val, 4, 11));
     break;

diff --git a/lld/test/ELF/aarch64-tlsld-ldst.s b/lld/test/ELF/aarch64-tlsld-ldst.s
new file mode 100644 (file)
index 0000000..0f9db77
--- /dev/null
+++ b/lld/test/ELF/aarch64-tlsld-ldst.s
@@ -0,0 +1,83 @@
+// RUN: llvm-mc -triple=aarch64-linux-gnu -filetype=obj %s -o %t.o
+// RUN: ld.lld %t.o -o %t
+// RUN: llvm-objdump -d %t | FileCheck %s
+// RUN: llvm-readelf --symbols %t | FileCheck -check-prefix CHECK-SYMS %s
+        .text
+        .globl _start
+        .type _start, %function
+_start:  mrs x8, TPIDR_EL0
+
+        add x8, x8, :tprel_hi12:var0
+        ldr q20, [x8, :tprel_lo12_nc:var0]
+
+        add x8, x8, :tprel_hi12:var1
+        ldr x0, [x8, :tprel_lo12_nc:var1]
+
+        add x8, x8, :tprel_hi12:var2
+        ldr w0, [x8, :tprel_lo12_nc:var2]
+
+        add x8, x8, :tprel_hi12:var3
+        ldrh w0, [x8, :tprel_lo12_nc:var3]
+
+        add x8, x8, :tprel_hi12:var4
+        ldrb w0, [x8, :tprel_lo12_nc:var4]
+
+// CHECK: _start:
+// CHECK-NEXT:    20000:       48 d0 3b d5     mrs     x8, TPIDR_EL0
+// 0x0 + c10 = 0xc10       = tcb (16-bytes) + var0
+// CHECK-NEXT:    20004:       08 01 40 91     add     x8, x8, #0, lsl #12
+// CHECK-NEXT:    20008:       14 05 c3 3d     ldr     q20, [x8, #3088]
+// 0x1000 + 0x820 = 0x1820 = tcb + var1
+// CHECK-NEXT:    2000c:       08 05 40 91     add     x8, x8, #1, lsl #12
+// CHECK-NEXT:    20010:       00 11 44 f9     ldr     x0, [x8, #2080]
+// 0x2000 + 0x428 = 0x2428 = tcb + var2
+// CHECK-NEXT:    20014:       08 09 40 91     add     x8, x8, #2, lsl #12
+// CHECK-NEXT:    20018:       00 29 44 b9     ldr     w0, [x8, #1064]
+// 0x3000 + 0x2c  = 0x302c = tcb + var3
+// CHECK-NEXT:    2001c:       08 0d 40 91     add     x8, x8, #3, lsl #12
+// CHECK-NEXT:    20020:       00 59 40 79     ldrh    w0, [x8, #44]
+// 0x3000 + 0xc2e = 0x32ce = tcb + var4
+// CHECK-NEXT:    20024:       08 0d 40 91     add     x8, x8, #3, lsl #12
+// CHECK-NEXT:    20028:       00 b9 70 39     ldrb    w0, [x8, #3118]
+
+// CHECK-SYMS:      0000000000000c00     0 TLS     GLOBAL DEFAULT    2 var0
+// CHECK-SYMS-NEXT: 0000000000001810     4 TLS     GLOBAL DEFAULT    2 var1
+// CHECK-SYMS-NEXT: 0000000000002418     2 TLS     GLOBAL DEFAULT    2 var2
+// CHECK-SYMS-NEXT: 000000000000301c     1 TLS     GLOBAL DEFAULT    2 var3
+// CHECK-SYMS-NEXT: 0000000000003c1e     0 TLS     GLOBAL DEFAULT    2 var4
+
+        .globl var0
+        .globl var1
+        .globl var2
+        .globl var3
+        .globl var4
+        .type var0,@object
+        .type var1,@object
+        .type var2,@object
+        .type var3,@object
+
+.section .tbss,"awT",@nobits
+        .balign 16
+        .space 1024 * 3
+var0:
+        .quad 0
+        .quad 0
+        .size var1, 16
+        .space 1024 * 3
+var1:
+        .quad 0
+        .size var1, 8
+        .space 1024 * 3
+var2:
+        .word 0
+        .size var1, 4
+
+        .space 1024 * 3
+var3:
+        .hword 0
+        .size var2, 2
+        .space 1024 * 3
+var4:
+        .byte 0
+        .size var3, 1
+        .space 1024 * 3