arm: dts: imx8mq: add MNT Reform 2

Device tree taken from Linux v5.16-rc5.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 086533b..5126ea8 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -918,6 +918,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
        imx8mq-evk.dtb \
        imx8mm-beacon-kit.dtb \
        imx8mn-beacon-kit.dtb \
+       imx8mq-mnt-reform2.dtb \
        imx8mq-phanbell.dtb \
        imx8mp-evk.dtb \
        imx8mp-phyboard-pollux-rdk.dtb \

diff --git a/arch/arm/dts/imx8mq-mnt-reform2.dts b/arch/arm/dts/imx8mq-mnt-reform2.dts
new file mode 100644 (file)
index 0000000..4f2db61
--- /dev/null
+++ b/arch/arm/dts/imx8mq-mnt-reform2.dts
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Copyright 2019-2021 MNT Research GmbH
+ * Copyright 2021 Lucas Stach <dev@lynxeye.de>
+ */
+
+/dts-v1/;
+
+#include "imx8mq-nitrogen-som.dtsi"
+
+/ {
+       model = "MNT Reform 2";
+       compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
+
+       pcie1_refclk: clock-pcie1-refclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <100000000>;
+       };
+
+       reg_main_5v: regulator-main-5v {
+               compatible = "regulator-fixed";
+               regulator-name = "5V";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+       };
+
+       reg_main_3v3: regulator-main-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+
+       reg_main_usb: regulator-main-usb {
+               compatible = "regulator-fixed";
+               regulator-name = "USB_PWR";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               vin-supply = <&reg_main_5v>;
+       };
+
+       sound {
+               compatible = "fsl,imx-audio-wm8960";
+               audio-cpu = <&sai2>;
+               audio-codec = <&wm8960>;
+               audio-routing =
+                       "Headphone Jack", "HP_L",
+                       "Headphone Jack", "HP_R",
+                       "Ext Spk", "SPK_LP",
+                       "Ext Spk", "SPK_LN",
+                       "Ext Spk", "SPK_RP",
+                       "Ext Spk", "SPK_RN",
+                       "LINPUT1", "Mic Jack",
+                       "Mic Jack", "MICB",
+                       "LINPUT2", "Line In Jack",
+                       "RINPUT2", "Line In Jack";
+               model = "wm8960-audio";
+       };
+};
+
+&fec1 {
+       status = "okay";
+};
+
+&i2c3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c3>;
+       status = "okay";
+
+       wm8960: codec@1a {
+               compatible = "wlf,wm8960";
+               reg = <0x1a>;
+               clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
+               clock-names = "mclk";
+               #sound-dai-cells = <0>;
+       };
+
+       rtc@68 {
+               compatible = "nxp,pcf8523";
+               reg = <0x68>;
+       };
+};
+
+&pcie1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcie1>;
+       reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
+       clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
+                <&clk IMX8MQ_CLK_PCIE2_AUX>,
+                <&clk IMX8MQ_CLK_PCIE2_PHY>,
+                <&pcie1_refclk>;
+       clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+       status = "okay";
+};
+
+&reg_1p8v {
+       vin-supply = <&reg_main_5v>;
+};
+
+&reg_snvs {
+       vin-supply = <&reg_main_5v>;
+};
+
+&reg_arm_dram {
+       vin-supply = <&reg_main_5v>;
+};
+
+&reg_dram_1p1v {
+       vin-supply = <&reg_main_5v>;
+};
+
+&reg_soc_gpu_vpu {
+       vin-supply = <&reg_main_5v>;
+};
+
+&sai2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sai2>;
+       assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
+       assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+       assigned-clock-rates = <25000000>;
+       fsl,sai-mclk-direction-output;
+       fsl,sai-asynchronous;
+       status = "okay";
+};
+
+&snvs_rtc {
+       status = "disabled";
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       status = "okay";
+};
+
+&usb3_phy0 {
+       vbus-supply = <&reg_main_usb>;
+       status = "okay";
+};
+
+&usb3_phy1 {
+       vbus-supply = <&reg_main_usb>;
+       status = "okay";
+};
+
+&usb_dwc3_0 {
+       dr_mode = "host";
+       status = "okay";
+};
+
+&usb_dwc3_1 {
+       dr_mode = "host";
+       status = "okay";
+};
+
+&usdhc2 {
+       assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
+       assigned-clock-rates = <200000000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc2>;
+       vqmmc-supply = <&reg_main_3v3>;
+       vmmc-supply = <&reg_main_3v3>;
+       bus-width = <4>;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl_i2c3: i2c3grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL                  0x4000007f
+                       MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA                  0x4000007f
+               >;
+       };
+
+       pinctrl_pcie1: pcie1grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23               0x16
+               >;
+       };
+
+       pinctrl_sai2: sai2grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0            0xd6
+                       MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC             0xd6
+                       MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK              0xd6
+                       MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC             0xd6
+                       MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK              0xd6
+                       MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK                0xd6
+                       MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0            0xd6
+               >;
+       };
+
+       pinctrl_uart2: uart2grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX             0x45
+                       MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX             0x45
+               >;
+       };
+
+       pinctrl_usdhc2: usdhc2grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B               0x0
+                       MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x83
+                       MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc3
+                       MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc3
+                       MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc3
+                       MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc3
+                       MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc3
+               >;
+       };
+};

diff --git a/arch/arm/dts/imx8mq-nitrogen-som.dtsi b/arch/arm/dts/imx8mq-nitrogen-som.dtsi
new file mode 100644 (file)
index 0000000..36fc428
--- /dev/null
+++ b/arch/arm/dts/imx8mq-nitrogen-som.dtsi
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018 Boundary Devices
+ * Copyright 2021 Lucas Stach <dev@lynxeye.de>
+ */
+
+#include "imx8mq.dtsi"
+
+/ {
+       model = "Boundary Devices i.MX8MQ Nitrogen8M";
+       compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
+
+       chosen {
+               stdout-path = &uart1;
+       };
+
+       reg_1p8v: regulator-fixed-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "1P8V";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+       };
+
+       reg_snvs: regulator-fixed-snvs {
+               compatible = "regulator-fixed";
+               regulator-name = "VDD_SNVS";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+};
+
+&{/opp-table/opp-800000000} {
+       opp-microvolt = <1000000>;
+};
+
+&{/opp-table/opp-1000000000} {
+       opp-microvolt = <1000000>;
+};
+
+&A53_0 {
+       cpu-supply = <&reg_arm_dram>;
+};
+
+&A53_1 {
+       cpu-supply = <&reg_arm_dram>;
+};
+
+&A53_2 {
+       cpu-supply = <&reg_arm_dram>;
+};
+
+&A53_3 {
+       cpu-supply = <&reg_arm_dram>;
+};
+
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec1>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy0>;
+       fsl,magic-packet;
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@4 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <4>;
+                       interrupt-parent = <&gpio1>;
+                       interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+               };
+       };
+};
+
+&i2c1 {
+       clock-frequency = <400000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       status = "okay";
+
+       i2c-mux@70 {
+               compatible = "nxp,pca9546";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_i2c1_pca9546>;
+               reg = <0x70>;
+               reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               i2c1a: i2c@0 {
+                       reg = <0>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       reg_arm_dram: regulator@60 {
+                               compatible = "fcs,fan53555";
+                               reg = <0x60>;
+                               regulator-name = "VDD_ARM_DRAM_1V";
+                               regulator-min-microvolt = <1000000>;
+                               regulator-max-microvolt = <1000000>;
+                               regulator-always-on;
+                       };
+               };
+
+               i2c1b: i2c@1 {
+                       reg = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       reg_dram_1p1v: regulator@60 {
+                               compatible = "fcs,fan53555";
+                               reg = <0x60>;
+                               regulator-name = "NVCC_DRAM_1P1V";
+                               regulator-min-microvolt = <1100000>;
+                               regulator-max-microvolt = <1100000>;
+                               regulator-always-on;
+                       };
+               };
+
+               i2c1c: i2c@2 {
+                       reg = <2>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       reg_soc_gpu_vpu: regulator@60 {
+                               compatible = "fcs,fan53555";
+                               reg = <0x60>;
+                               regulator-name = "VDD_SOC_GPU_VPU";
+                               regulator-min-microvolt = <900000>;
+                               regulator-max-microvolt = <900000>;
+                               regulator-always-on;
+                       };
+               };
+
+               i2c1d: i2c@3 {
+                       reg = <3>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+       };
+};
+
+&pgc_gpu {
+       power-supply = <&reg_soc_gpu_vpu>;
+};
+
+&pgc_vpu {
+       power-supply = <&reg_soc_gpu_vpu>;
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       status = "okay";
+};
+
+&usdhc1 {
+       assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+       assigned-clock-rates = <400000000>;
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+       vqmmc-supply = <&reg_1p8v>;
+       vmmc-supply = <&reg_snvs>;
+       bus-width = <8>;
+       non-removable;
+       no-mmc-hs400;
+       no-sdio;
+       no-sd;
+       status = "okay";
+};
+
+&wdog1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_wdog>;
+       fsl,ext-reset-output;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl_fec1: fec1grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
+                       MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO               0x23
+                       MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
+                       MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
+                       MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
+                       MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
+                       MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
+                       MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
+                       MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
+                       MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
+                       MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
+                       MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
+                       MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
+                       MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
+                       MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x19
+                       MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11              0x59
+               >;
+       };
+
+       pinctrl_i2c1: i2c1grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL                  0x4000007f
+                       MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA                  0x4000007f
+               >;
+       };
+
+       pinctrl_i2c1_pca9546: i2c1-pca9546grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8               0x49
+               >;
+       };
+
+       pinctrl_uart1: uart1grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX             0x45
+                       MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX             0x45
+               >;
+       };
+
+       pinctrl_usdhc1: usdhc1grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x83
+                       MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc3
+                       MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc3
+                       MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc3
+                       MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc3
+                       MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc3
+                       MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc3
+                       MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc3
+                       MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc3
+                       MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc3
+                       MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
+               >;
+       };
+
+       pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x8d
+                       MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xcd
+                       MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xcd
+                       MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xcd
+                       MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xcd
+                       MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xcd
+                       MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xcd
+                       MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xcd
+                       MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xcd
+                       MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xcd
+               >;
+       };
+
+       pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x9f
+                       MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xdf
+                       MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xdf
+                       MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xdf
+                       MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xdf
+                       MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xdf
+                       MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xdf
+                       MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xdf
+                       MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xdf
+                       MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xdf
+               >;
+       };
+
+       pinctrl_wdog: wdoggrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
+               >;
+       };
+};