Use isPhysical/isVirtual methods.
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D141715
continue;
// If this is a virtual register, only clobber it since it doesn't
// have aliases.
- if (Register::isVirtualRegister(MO.getReg()))
+ if (MO.getReg().isVirtual())
clobberRegisterUses(RegVars, MO.getReg(), DbgValues, LiveEntries,
MI);
// If this is a register def operand, it may end a debug value
return;
for (const MachineOperand &MO : MI.operands()) {
- if (MO.isReg() && MO.isDef() &&
- Register::isPhysicalRegister(MO.getReg())) {
+ if (MO.isReg() && MO.isDef() && MO.getReg().isPhysical()) {
for (auto &FwdReg : ForwardedRegWorklist)
if (TRI.regsOverlap(FwdReg.first, MO.getReg()))
Defs.insert(FwdReg.first);
// the callee.
const MachineOperand &CalleeOp = TII->getCalleeOperand(MI);
if (!CalleeOp.isGlobal() &&
- (!CalleeOp.isReg() ||
- !Register::isPhysicalRegister(CalleeOp.getReg())))
+ (!CalleeOp.isReg() || !CalleeOp.getReg().isPhysical()))
continue;
unsigned CallReg = 0;
bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
llvm::Register MachineReg,
unsigned MaxSize) {
- if (!llvm::Register::isPhysicalRegister(MachineReg)) {
+ if (!MachineReg.isPhysical()) {
if (isFrameRegister(TRI, MachineReg)) {
DwarfRegs.push_back(Register::createRegister(-1, nullptr));
return true;
addRegAndItsAliases(Reg, TRI, Uses);
} else {
if (Uses.erase(Reg)) {
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
Uses.erase(*SubRegs); // Use sub-registers to be conservative
}
if (!HReg)
return 0;
- if (Register::isVirtualRegister(HReg))
+ if (HReg.isVirtual())
return Sub == HSub ? HReg : Register();
const TargetRegisterClass *RC = MRI.getRegClass(Reg);
// If the original (pre-splitting) registers match this
// copy came from a split.
- if (!Register::isVirtualRegister(Reg) || VRM.getOriginal(Reg) != Original)
+ if (!Reg.isVirtual() || VRM.getOriginal(Reg) != Original)
return false;
// Follow the copy live-in value.
// Make sure that the copy dest is not a vreg when the copy source is a
// physical register.
- if (!OPI2->isReg() || (!Register::isPhysicalRegister(OPI->getReg()) &&
- Register::isPhysicalRegister(OPI2->getReg())))
+ if (!OPI2->isReg() ||
+ (!OPI->getReg().isPhysical() && OPI2->getReg().isPhysical()))
return false;
return true;
if (!MO.readsReg())
return;
Register MOReg = MO.getReg();
- if (!Register::isVirtualRegister(MOReg))
+ if (!MOReg.isVirtual())
return;
unsigned MOSubReg = MO.getSubReg();
void DetectDeadLanes::transferUsedLanesStep(const MachineInstr &MI,
LaneBitmask UsedLanes) {
for (const MachineOperand &MO : MI.uses()) {
- if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
+ if (!MO.isReg() || !MO.getReg().isVirtual())
continue;
LaneBitmask UsedOnMO = transferUsedLanes(MI, UsedLanes, MO);
addUsedLanesOnOperand(MO, UsedOnMO);
return;
const MachineOperand &Def = *MI.defs().begin();
Register DefReg = Def.getReg();
- if (!Register::isVirtualRegister(DefReg))
+ if (!DefReg.isVirtual())
return;
unsigned DefRegIdx = Register::virtReg2Index(DefReg);
if (!DefinedByCopy.test(DefRegIdx))
continue;
LaneBitmask MODefinedLanes;
- if (Register::isPhysicalRegister(MOReg)) {
+ if (MOReg.isPhysical()) {
MODefinedLanes = LaneBitmask::getAll();
} else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) {
MODefinedLanes = LaneBitmask::getAll();
} else {
- assert(Register::isVirtualRegister(MOReg));
+ assert(MOReg.isVirtual());
if (MRI->hasOneDef(MOReg)) {
const MachineOperand &MODef = *MRI->def_begin(MOReg);
const MachineInstr &MODefMI = *MODef.getParent();
Register DefReg = Def.getReg();
// The used lanes of COPY-like instruction operands are determined by the
// following dataflow analysis.
- if (Register::isVirtualRegister(DefReg)) {
+ if (DefReg.isVirtual()) {
// But ignore copies across incompatible register classes.
bool CrossCopy = false;
if (lowersToCopies(UseMI)) {
return false;
const MachineOperand &Def = MI.getOperand(0);
Register DefReg = Def.getReg();
- if (!Register::isVirtualRegister(DefReg))
+ if (!DefReg.isVirtual())
return false;
unsigned DefRegIdx = Register::virtReg2Index(DefReg);
if (!DefinedByCopy.test(DefRegIdx))
return false;
Register MOReg = MO.getReg();
- if (Register::isVirtualRegister(MOReg)) {
+ if (MOReg.isVirtual()) {
const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
*CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO);
}
if (!MO.isReg())
continue;
Register Reg = MO.getReg();
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
continue;
unsigned RegIdx = Register::virtReg2Index(Reg);
const VRegInfo &RegInfo = VRegInfos[RegIdx];
Register Reg = MO.getReg();
// Remember clobbered regunits.
- if (MO.isDef() && Register::isPhysicalRegister(Reg))
+ if (MO.isDef() && Reg.isPhysical())
for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
++Units)
ClobberedRegUnits.set(*Units);
- if (!MO.readsReg() || !Register::isVirtualRegister(Reg))
+ if (!MO.readsReg() || !Reg.isVirtual())
continue;
MachineInstr *DefMI = MRI->getVRegDef(Reg);
if (!DefMI || DefMI->getParent() != Head)
if (!MO.isReg())
continue;
Register Reg = MO.getReg();
- if (!Register::isPhysicalRegister(Reg))
+ if (!Reg.isPhysical())
continue;
// I clobbers Reg, so it isn't live before I.
if (MO.isDef())
assert(SubIdx != 0 && "Invalid index for insert_subreg");
Register DstSubReg = TRI->getSubReg(DstReg, SubIdx);
- assert(Register::isPhysicalRegister(DstReg) &&
+ assert(DstReg.isPhysical() &&
"Insert destination must be in a physical register");
- assert(Register::isPhysicalRegister(InsReg) &&
+ assert(InsReg.isPhysical() &&
"Inserted value must be in a physical register");
LLVM_DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
continue;
Register SrcReg = MI.getOperand(1).getReg();
Register DstReg = MI.getOperand(0).getReg();
- if (Register::isVirtualRegister(SrcReg) &&
- Register::isVirtualRegister(DstReg)) {
+ if (SrcReg.isVirtual() && DstReg.isVirtual()) {
auto SrcRC = MRI.getRegClass(SrcReg);
auto DstRC = MRI.getRegClass(DstReg);
if (SrcRC == DstRC) {
if (MO.isDef())
std::swap(Src, Dst);
- assert((RepairPt.getNumInsertPoints() == 1 ||
- Register::isPhysicalRegister(Dst)) &&
+ assert((RepairPt.getNumInsertPoints() == 1 || Dst.isPhysical()) &&
"We are about to create several defs for Dst");
// Build the instruction used to repair, then clone it at the right
// Check if this is a physical or virtual register.
Register Reg = MO.getReg();
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
// We are going to split every outgoing edges.
// Check that this is possible.
// FIXME: The machine representation is currently broken
const TargetRegisterClass &RegClass, MachineOperand &RegMO) {
Register Reg = RegMO.getReg();
// Assume physical registers are properly constrained.
- assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
+ assert(Reg.isVirtual() && "PhysReg not implemented");
// Save the old register class to check whether
// the change notifications will be required.
MachineOperand &RegMO, unsigned OpIdx) {
Register Reg = RegMO.getReg();
// Assume physical registers are properly constrained.
- assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
+ assert(Reg.isVirtual() && "PhysReg not implemented");
const TargetRegisterClass *OpRC = TII.getRegClass(II, OpIdx, &TRI, MF);
// Some of the target independent instructions, like COPY, may not impose any
Register Reg = MO.getReg();
// Physical registers don't need to be constrained.
- if (Register::isPhysicalRegister(Reg))
+ if (Reg.isPhysical())
continue;
// Register operands with a value of 0 (e.g. predicate operands) don't need
continue;
Register Reg = MO.getReg();
- if (Register::isPhysicalRegister(Reg) || !MRI.use_nodbg_empty(Reg))
+ if (Reg.isPhysical() || !MRI.use_nodbg_empty(Reg))
return false;
}
return true;
break;
case TargetOpcode::COPY:
VReg = MI->getOperand(1).getReg();
- if (Register::isPhysicalRegister(VReg))
+ if (VReg.isPhysical())
return std::nullopt;
break;
case TargetOpcode::G_INTTOPTR:
static void getVDefInterval(const MachineInstr &MI, LiveIntervals &LIS) {
for (const MachineOperand &MO : MI.operands())
- if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
+ if (MO.isReg() && MO.isDef() && MO.getReg().isVirtual())
LIS.getInterval(MO.getReg());
}
if (!MO->isReg())
continue;
Register Reg = MO->getReg();
- if (!Reg || Register::isVirtualRegister(Reg) || MRI.isReserved(Reg)) {
+ if (!Reg || Reg.isVirtual() || MRI.isReserved(Reg)) {
continue;
}
// Skip non-Defs, including undef uses and internal reads.
SmallVector<const MachineOperand *, 4> RegMaskPtrs;
for (const MachineOperand &MO : MI.operands()) {
// Determine whether the operand is a register def.
- if (MO.isReg() && MO.isDef() && MO.getReg() &&
- Register::isPhysicalRegister(MO.getReg()) &&
+ if (MO.isReg() && MO.isDef() && MO.getReg() && MO.getReg().isPhysical() &&
!IgnoreSPAlias(MO.getReg())) {
// Remove ranges of all aliased registers.
for (MCRegAliasIterator RAI(MO.getReg(), TRI, true); RAI.isValid(); ++RAI)
SmallVector<const uint32_t *, 4> RegMasks;
for (const MachineOperand &MO : MI.operands()) {
// Determine whether the operand is a register def.
- if (MO.isReg() && MO.isDef() && MO.getReg() &&
- Register::isPhysicalRegister(MO.getReg()) &&
+ if (MO.isReg() && MO.isDef() && MO.getReg() && MO.getReg().isPhysical() &&
!(MI.isCall() && MO.getReg() == SP)) {
// Remove ranges of all aliased registers.
for (MCRegAliasIterator RAI(MO.getReg(), TRI, true); RAI.isValid(); ++RAI)
static void collectRegDefs(const MachineInstr &MI, DefinedRegsSet &Regs,
const TargetRegisterInfo *TRI) {
for (const MachineOperand &MO : MI.operands()) {
- if (MO.isReg() && MO.isDef() && MO.getReg() &&
- Register::isPhysicalRegister(MO.getReg())) {
+ if (MO.isReg() && MO.isDef() && MO.getReg() && MO.getReg().isPhysical()) {
Regs.insert(MO.getReg());
for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
Regs.insert(*AI);
void UserValue::mapVirtRegs(LDVImpl *LDV) {
for (unsigned i = 0, e = locations.size(); i != e; ++i)
- if (locations[i].isReg() &&
- Register::isVirtualRegister(locations[i].getReg()))
+ if (locations[i].isReg() && locations[i].getReg().isVirtual())
LDV->mapVirtReg(locations[i].getReg(), this);
}
}
void LDVImpl::mapVirtReg(Register VirtReg, UserValue *EC) {
- assert(Register::isVirtualRegister(VirtReg) && "Only map VirtRegs");
+ assert(VirtReg.isVirtual() && "Only map VirtRegs");
UserValue *&Leader = virtRegToEqClass[VirtReg];
Leader = UserValue::merge(Leader, EC);
}
// will be incorrect.
bool Discard = false;
for (const MachineOperand &Op : MI.debug_operands()) {
- if (Op.isReg() && Register::isVirtualRegister(Op.getReg())) {
+ if (Op.isReg() && Op.getReg().isVirtual()) {
const Register Reg = Op.getReg();
if (!LIS->hasInterval(Reg)) {
// The DBG_VALUE is described by a virtual register that does not have a
SmallVectorImpl<std::pair<SlotIndex, DbgVariableValue>> &NewDefs,
MachineRegisterInfo &MRI, LiveIntervals &LIS) {
// Don't track copies from physregs, there are too many uses.
- if (any_of(LocIntervals, [](auto LocI) {
- return !Register::isVirtualRegister(LocI.second->reg());
- }))
+ if (any_of(LocIntervals,
+ [](auto LocI) { return !LocI.second->reg().isVirtual(); }))
return;
// Collect all the (vreg, valno) pairs that are copies of LI.
// arguments, and the argument registers are always call clobbered. We are
// better off in the source register which could be a callee-saved
// register, or it could be spilled.
- if (!Register::isVirtualRegister(DstReg))
+ if (!DstReg.isVirtual())
continue;
// Is the value extended to reach this copy? If not, another def may be
bool ShouldExtendDef = false;
for (unsigned LocNo : DbgValue.loc_nos()) {
const MachineOperand &LocMO = locations[LocNo];
- if (!LocMO.isReg() || !Register::isVirtualRegister(LocMO.getReg())) {
+ if (!LocMO.isReg() || !LocMO.getReg().isVirtual()) {
ShouldExtendDef |= !LocMO.isReg();
continue;
}
unsigned SpillOffset = 0;
MachineOperand Loc = locations[I];
// Only virtual registers are rewritten.
- if (Loc.isReg() && Loc.getReg() &&
- Register::isVirtualRegister(Loc.getReg())) {
+ if (Loc.isReg() && Loc.getReg() && Loc.getReg().isVirtual()) {
Register VirtReg = Loc.getReg();
if (VRM.isAssignedReg(VirtReg) &&
Register::isPhysicalRegister(VRM.getPhys(VirtReg))) {
LaneBitmask LaneMask,
const MachineRegisterInfo &MRI,
const SlotIndexes &Indexes) const {
- assert(Register::isVirtualRegister(reg()));
+ assert(reg().isVirtual());
LaneBitmask VRegMask = MRI.getMaxLaneMaskForVReg(reg());
assert((VRegMask & LaneMask).any());
const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
#endif
LiveInterval *LiveIntervals::createInterval(Register reg) {
- float Weight = Register::isPhysicalRegister(reg) ? huge_valf : 0.0F;
+ float Weight = reg.isPhysical() ? huge_valf : 0.0F;
return new LiveInterval(reg, Weight);
}
bool LiveIntervals::shrinkToUses(LiveInterval *li,
SmallVectorImpl<MachineInstr*> *dead) {
LLVM_DEBUG(dbgs() << "Shrink: " << *li << '\n');
- assert(Register::isVirtualRegister(li->reg()) &&
- "Can only shrink virtual registers");
+ assert(li->reg().isVirtual() && "Can only shrink virtual registers");
// Shrink subregister live ranges.
bool NeedsCleanup = false;
void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, Register Reg) {
LLVM_DEBUG(dbgs() << "Shrink: " << SR << '\n');
- assert(Register::isVirtualRegister(Reg) &&
- "Can only shrink virtual registers");
+ assert(Reg.isVirtual() && "Can only shrink virtual registers");
// Find all the values used, including PHI kills.
ShrinkToUsesWorkList WorkList;
Register Reg = MO.getReg();
if (!Reg)
continue;
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
LiveInterval &LI = LIS.getInterval(Reg);
if (LI.hasSubRanges()) {
unsigned SubReg = MO.getSubReg();
return;
LLVM_DEBUG({
dbgs() << " ";
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
dbgs() << printReg(Reg);
if (LaneMask.any())
dbgs() << " L" << PrintLaneMask(LaneMask);
// Return the last use of reg between NewIdx and OldIdx.
SlotIndex findLastUseBefore(SlotIndex Before, Register Reg,
LaneBitmask LaneMask) {
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
SlotIndex LastUse = Before;
for (MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
if (MO.isUndef())
// Check if MII uses Reg.
for (MIBundleOperands MO(*MII); MO.isValid(); ++MO)
- if (MO->isReg() && !MO->isUndef() &&
- Register::isPhysicalRegister(MO->getReg()) &&
+ if (MO->isReg() && !MO->isUndef() && MO->getReg().isPhysical() &&
TRI.hasRegUnit(MO->getReg(), Reg))
return Idx.getRegSlot();
}
// We can't remat physreg uses, unless it is a constant or target wants
// to ignore this use.
- if (Register::isPhysicalRegister(MO.getReg())) {
+ if (MO.getReg().isPhysical()) {
if (MRI.isConstantPhysReg(MO.getReg()) || TII.isIgnorableUse(MO))
continue;
return false;
if (!MO.isReg())
continue;
Register Reg = MO.getReg();
- if (!Register::isVirtualRegister(Reg)) {
+ if (!Reg.isVirtual()) {
// Check if MI reads any unreserved physregs.
if (Reg && MO.readsReg() && !MRI.isReserved(Reg))
ReadsPhysRegs = true;
// Remove all operands that aren't physregs.
for (unsigned i = MI->getNumOperands(); i; --i) {
const MachineOperand &MO = MI->getOperand(i-1);
- if (MO.isReg() && Register::isPhysicalRegister(MO.getReg()))
+ if (MO.isReg() && MO.getReg().isPhysical())
continue;
MI->removeOperand(i-1);
}
Register Reg = MO.getReg();
// Do not move the instruction if it def/uses a physical register,
// unless it is a constant physical register or a noreg.
- if (!Register::isVirtualRegister(Reg)) {
+ if (!Reg.isVirtual()) {
if (!Reg || MRI.isConstantPhysReg(Reg))
continue;
Insert = nullptr;
continue;
Register MOReg = MO.getReg();
if (MO.isUse()) {
- if (!(Register::isPhysicalRegister(MOReg) && MRI->isReserved(MOReg)))
+ if (!(MOReg.isPhysical() && MRI->isReserved(MOReg)))
MO.setIsKill(false);
if (MO.readsReg())
UseRegs.push_back(MOReg);
assert(MO.isDef());
// FIXME: We should not remove any dead flags. However the MIPS RDDSP
// instruction needs it at the moment: http://llvm.org/PR27116.
- if (Register::isPhysicalRegister(MOReg) && !MRI->isReserved(MOReg))
+ if (MOReg.isPhysical() && !MRI->isReserved(MOReg))
MO.setIsDead(false);
DefRegs.push_back(MOReg);
}
if (MO.isReg() && MO.isKill()) {
MO.setIsKill(false);
Register Reg = MO.getReg();
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
bool removed = getVarInfo(Reg).removeKill(MI);
assert(removed && "kill not in register's VarInfo?");
(void)removed;
// Record all vreg defs and kills of all instructions in SuccBB.
for (; BBI != BBE; ++BBI) {
for (const MachineOperand &Op : BBI->operands()) {
- if (Op.isReg() && Register::isVirtualRegister(Op.getReg())) {
+ if (Op.isReg() && Op.getReg().isVirtual()) {
if (Op.isDef())
Defs.insert(Op.getReg());
else if (Op.isKill())
if (!MO.isReg())
continue;
- if (Register::isVirtualRegister(MO.getReg()))
+ if (MO.getReg().isVirtual())
continue;
if (!MO.isDef())
continue;
MachineOperand &MO = II->getOperand(0);
- if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
+ if (!MO.isReg() || !MO.getReg().isVirtual())
continue;
if (!MO.isDef())
continue;
}
if (II->getOperand(i).isReg()) {
- if (!Register::isVirtualRegister(II->getOperand(i).getReg()))
+ if (!II->getOperand(i).getReg().isVirtual())
if (!llvm::is_contained(PhysRegDefs, II->getOperand(i).getReg())) {
continue;
}
const Register Dst = MI->getOperand(0).getReg();
const Register Src = MI->getOperand(1).getReg();
- if (!Register::isVirtualRegister(Dst))
+ if (!Dst.isVirtual())
continue;
- if (!Register::isVirtualRegister(Src))
+ if (!Src.isVirtual())
continue;
// Not folding COPY instructions if regbankselect has not set the RCs.
// Why are we only considering Register Classes? Because the verifier
static std::string getRegisterName(const TargetRegisterInfo *TRI,
Register Reg) {
- assert(Register::isPhysicalRegister(Reg) && "expected phys reg");
+ assert(Reg.isPhysical() && "expected phys reg");
return StringRef(TRI->getName(Reg)).lower();
}
if (Token.is(MIToken::dot)) {
if (parseSubRegisterIndex(SubReg))
return true;
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
return error("subregister index expects a virtual register");
}
if (Token.is(MIToken::colon)) {
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
return error("register class specification expects a virtual register");
lex();
if (parseRegisterClassOrBank(*RegInfo))
}
} else if (consumeIfPresent(MIToken::lparen)) {
// Virtual registers may have a tpe with GlobalISel.
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
return error("unexpected type on physical register");
LLT Ty;
MRI.setRegClassOrRegBank(Reg, static_cast<RegisterBank *>(nullptr));
MRI.setType(Reg, Ty);
- } else if (Register::isVirtualRegister(Reg)) {
+ } else if (Reg.isVirtual()) {
// Generic virtual registers must have a type.
// If we end up here this means the type hasn't been specified and
// this is bad!
MO.getType(), MO.getTargetFlags(),
MO.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue());
case MachineOperand::MO_Register:
- if (Register::isVirtualRegister(MO.getReg()))
+ if (MO.getReg().isVirtual())
return MRI.getVRegDef(MO.getReg())->getOpcode();
return MO.getReg();
case MachineOperand::MO_Immediate:
// Look for instructions that define VRegs in operand 0.
MachineOperand &MO = Candidate.getOperand(0);
// Avoid non regs, instructions defining physical regs.
- if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
+ if (!MO.isReg() || !MO.getReg().isVirtual())
continue;
VRegs.push_back(
NamedVReg(MO.getReg(), Prefix + getInstructionOpcodeHash(Candidate)));
return false;
InterferingIntervals.append(IFIntervals.begin(), IFIntervals.end());
for (const LiveInterval *Intf : reverse(IFIntervals)) {
- assert(Register::isVirtualRegister(Intf->reg()) &&
+ assert(Intf->reg().isVirtual() &&
"Only expecting virtual register interference from query");
// This is the same set of legality checks as in the default case: don't
// try to evict fixed regs or 'done' ones. Also don't break cascades,
MO.isUndef())
continue;
Register Reg = MO.getReg();
- if (Register::isPhysicalRegister(Reg) ||
- LV->getVarInfo(Reg).removeKill(MI)) {
+ if (Reg.isPhysical() || LV->getVarInfo(Reg).removeKill(MI)) {
KilledRegs.push_back(Reg);
LLVM_DEBUG(dbgs() << "Removing terminator kill: " << MI);
MO.setIsKill(false);
for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
if (!(--I)->addRegisterKilled(Reg, TRI, /* AddIfNotFound= */ false))
continue;
- if (Register::isVirtualRegister(Reg))
+ if (Reg.isVirtual())
LV->getVarInfo(Reg).Kills.push_back(&*I);
LLVM_DEBUG(dbgs() << "Restored terminator kill: " << *I);
break;
if (!MO.isReg() || !MO.isUse())
continue;
Register Reg = MO.getReg();
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
continue;
bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg);
MachineInstr *DefMI = MRI->getVRegDef(Reg);
if (!DefMI->isCopy())
continue;
Register SrcReg = DefMI->getOperand(1).getReg();
- if (!Register::isVirtualRegister(SrcReg))
+ if (!SrcReg.isVirtual())
continue;
if (DefMI->getOperand(0).getSubReg())
continue;
Register Reg = MO.getReg();
if (!Reg)
continue;
- if (Register::isVirtualRegister(Reg))
+ if (Reg.isVirtual())
continue;
// Reading either caller preserved or constant physregs is ok.
if (!isCallerPreservedOrConstPhysReg(Reg.asMCReg(), MO, *MI->getMF(), *TRI,
Register Reg = MO.getReg();
if (!Reg)
continue;
- if (Register::isVirtualRegister(Reg))
+ if (Reg.isVirtual())
continue;
// Check against PhysRefs even if the def is "dead".
if (PhysRefs.count(Reg.asMCReg()))
if (!MO.isReg() || !MO.isDef())
continue;
Register MOReg = MO.getReg();
- if (Register::isVirtualRegister(MOReg))
+ if (MOReg.isVirtual())
continue;
if (PhysRefs.count(MOReg.asMCReg()))
return false;
// If CSReg is used at all uses of Reg, CSE should not increase register
// pressure of CSReg.
bool MayIncreasePressure = true;
- if (Register::isVirtualRegister(CSReg) && Register::isVirtualRegister(Reg)) {
+ if (CSReg.isVirtual() && Reg.isVirtual()) {
MayIncreasePressure = false;
SmallPtrSet<MachineInstr*, 8> CSUses;
int NumOfUses = 0;
// of the redundant computation are copies, do not cse.
bool HasVRegUse = false;
for (const MachineOperand &MO : MI->operands()) {
- if (MO.isReg() && MO.isUse() && Register::isVirtualRegister(MO.getReg())) {
+ if (MO.isReg() && MO.isUse() && MO.getReg().isVirtual()) {
HasVRegUse = true;
break;
}
continue;
}
- assert(Register::isVirtualRegister(OldReg) &&
- Register::isVirtualRegister(NewReg) &&
+ assert(OldReg.isVirtual() && NewReg.isVirtual() &&
"Do not CSE physical register defs!");
if (!isProfitableToCSE(NewReg, OldReg, CSMI->getParent(), &MI)) {
return false;
for (const MachineOperand &MO : MI->operands()) {
- if (MO.isReg() && !Register::isVirtualRegister(MO.getReg())) {
+ if (MO.isReg() && !MO.getReg().isVirtual()) {
if (MO.isDef())
return false;
else
MachineInstr *MachineCombiner::getOperandDef(const MachineOperand &MO) {
MachineInstr *DefInstr = nullptr;
// We need a virtual register definition.
- if (MO.isReg() && Register::isVirtualRegister(MO.getReg()))
+ if (MO.isReg() && MO.getReg().isVirtual())
DefInstr = MRI->getUniqueVRegDef(MO.getReg());
// PHI's have no depth etc.
if (DefInstr && DefInstr->isPHI())
unsigned IDepth = 0;
for (const MachineOperand &MO : InstrPtr->operands()) {
// Check for virtual register operand.
- if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
+ if (!(MO.isReg() && MO.getReg().isVirtual()))
continue;
if (!MO.isUse())
continue;
for (const MachineOperand &MO : NewRoot->operands()) {
// Check for virtual register operand.
- if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
+ if (!(MO.isReg() && MO.getReg().isVirtual()))
continue;
if (!MO.isDef())
continue;
// An instruction that uses or defines a physical register can't e.g. be
// hoisted, so mark this as not invariant.
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
if (MO.isUse()) {
// If the physreg has no defs anywhere, it's just an ambient register
// and we can freely move its uses. Alternatively, if it's allocatable,
if (Check == IgnoreDefs)
continue;
else if (Check == IgnoreVRegDefs) {
- if (!Register::isVirtualRegister(MO.getReg()) ||
- !Register::isVirtualRegister(OMO.getReg()))
+ if (!MO.getReg().isVirtual() || !OMO.getReg().isVirtual())
if (!MO.isIdenticalTo(OMO))
return false;
} else {
int
MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
const TargetRegisterInfo *TRI) const {
- bool isPhys = Register::isPhysicalRegister(Reg);
+ bool isPhys = Reg.isPhysical();
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
// Accept regmask operands when Overlap is set.
continue;
Register MOReg = MO.getReg();
bool Found = (MOReg == Reg);
- if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
+ if (!Found && TRI && isPhys && MOReg.isPhysical()) {
if (Overlap)
Found = TRI->regsOverlap(MOReg, Reg);
else
void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
unsigned SubIdx,
const TargetRegisterInfo &RegInfo) {
- if (Register::isPhysicalRegister(ToReg)) {
+ if (ToReg.isPhysical()) {
if (SubIdx)
ToReg = RegInfo.getSubReg(ToReg, SubIdx);
for (MachineOperand &MO : operands()) {
bool MachineInstr::addRegisterKilled(Register IncomingReg,
const TargetRegisterInfo *RegInfo,
bool AddIfNotFound) {
- bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
+ bool isPhysReg = IncomingReg.isPhysical();
bool hasAliases = isPhysReg &&
MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
bool Found = false;
MO.setIsKill();
Found = true;
}
- } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
+ } else if (hasAliases && MO.isKill() && Reg.isPhysical()) {
// A super-register kill already exists.
if (RegInfo->isSuperRegister(IncomingReg, Reg))
return true;
void MachineInstr::clearRegisterKills(Register Reg,
const TargetRegisterInfo *RegInfo) {
- if (!Register::isPhysicalRegister(Reg))
+ if (!Reg.isPhysical())
RegInfo = nullptr;
for (MachineOperand &MO : operands()) {
if (!MO.isReg() || !MO.isUse() || !MO.isKill())
bool MachineInstr::addRegisterDead(Register Reg,
const TargetRegisterInfo *RegInfo,
bool AddIfNotFound) {
- bool isPhysReg = Register::isPhysicalRegister(Reg);
+ bool isPhysReg = Reg.isPhysical();
bool hasAliases = isPhysReg &&
MCRegAliasIterator(Reg, RegInfo, false).isValid();
bool Found = false;
if (MOReg == Reg) {
MO.setIsDead();
Found = true;
- } else if (hasAliases && MO.isDead() &&
- Register::isPhysicalRegister(MOReg)) {
+ } else if (hasAliases && MO.isDead() && MOReg.isPhysical()) {
// There exists a super-register that's marked dead.
if (RegInfo->isSuperRegister(Reg, MOReg))
return true;
void MachineInstr::addRegisterDefined(Register Reg,
const TargetRegisterInfo *RegInfo) {
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
if (MO)
return;
HashComponents.reserve(MI->getNumOperands() + 1);
HashComponents.push_back(MI->getOpcode());
for (const MachineOperand &MO : MI->operands()) {
- if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
+ if (MO.isReg() && MO.isDef() && MO.getReg().isVirtual())
continue; // Skip virtual register defs.
HashComponents.push_back(hash_value(MO));
DeadDefSet.erase(Reg);
}
- if (!MO.isDead() && Register::isPhysicalRegister(Reg)) {
+ if (!MO.isDead() && Reg.isPhysical()) {
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
unsigned SubReg = *SubRegs;
if (LocalDefSet.insert(SubReg).second)
continue;
Register MOReg = MO.getReg();
- if (!MOReg || !Register::isPhysicalRegister(MOReg))
+ if (!MOReg || !MOReg.isPhysical())
continue;
if (!TRI->regsOverlap(MOReg, Reg))
Register Reg = MO.getReg();
if (!Reg)
continue;
- assert(Register::isPhysicalRegister(Reg) &&
- "Not expecting virtual register!");
+ assert(Reg.isPhysical() && "Not expecting virtual register!");
if (!MO.isDef()) {
if (Reg && (PhysRegDefs.test(Reg) || PhysRegClobbers.test(Reg)))
if (!MO.isReg() || MO.isImplicit())
continue;
Register Reg = MO.getReg();
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
continue;
// FIXME: It seems bad to use RegSeen only for some of these calculations.
Register Reg = MO.getReg();
// If operand is a virtual register, check if it comes from a copy of a
// physical register.
- if (Register::isVirtualRegister(Reg))
+ if (Reg.isVirtual())
Reg = TRI->lookThruCopyLike(MO.getReg(), MRI);
- if (Register::isVirtualRegister(Reg))
+ if (Reg.isVirtual())
return false;
if (!TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *MI.getMF()))
return false;
const MachineFunction *MF = MI.getMF();
// Check that we are copying a constant physical register.
Register CopySrcReg = MI.getOperand(1).getReg();
- if (Register::isVirtualRegister(CopySrcReg))
+ if (CopySrcReg.isVirtual())
return false;
if (!TRI->isCallerPreservedPhysReg(CopySrcReg.asMCReg(), *MF))
Register CopyDstReg = MI.getOperand(0).getReg();
// Check if any of the uses of the copy are invariant stores.
- assert(Register::isVirtualRegister(CopyDstReg) &&
- "copy dst is not a virtual reg");
+ assert(CopyDstReg.isVirtual() && "copy dst is not a virtual reg");
for (MachineInstr &UseMI : MRI->use_instructions(CopyDstReg)) {
if (UseMI.mayStore() && isInvariantStore(UseMI, TRI, MRI))
if (!MO.isReg() || !MO.isDef())
continue;
Register Reg = MO.getReg();
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
continue;
for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
// A PHI may cause a copy to be inserted.
continue;
--NumDefs;
Register Reg = DefMO.getReg();
- if (Register::isPhysicalRegister(Reg))
+ if (Reg.isPhysical())
continue;
if (!TII->hasLowDefLatency(SchedModel, MI, i))
if (!MO.isReg() || MO.isImplicit())
continue;
Register Reg = MO.getReg();
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
continue;
if (MO.isDef() && HasHighOperandLatency(MI, i, Reg)) {
LLVM_DEBUG(dbgs() << "Hoist High Latency: " << MI);
const MachineOperand &MO = MI->getOperand(i);
// Physical registers may not differ here.
- assert((!MO.isReg() || MO.getReg() == 0 ||
- !Register::isPhysicalRegister(MO.getReg()) ||
+ assert((!MO.isReg() || MO.getReg() == 0 || !MO.getReg().isPhysical() ||
MO.getReg() == Dup->getOperand(i).getReg()) &&
"Instructions with different phys regs are not identical!");
- if (MO.isReg() && MO.isDef() &&
- !Register::isPhysicalRegister(MO.getReg()))
+ if (MO.isReg() && MO.isDef() && !MO.getReg().isPhysical())
Defs.push_back(i);
}
// An instruction that uses or defines a physical register can't e.g. be
// hoisted, so mark this as not invariant.
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
if (MO.isUse()) {
// If the physreg has no defs anywhere, it's just an ambient register
// and we can freely move its uses. Alternatively, if it's allocatable,
bool MachineOperand::isRenamable() const {
assert(isReg() && "Wrong MachineOperand accessor");
- assert(Register::isPhysicalRegister(getReg()) &&
+ assert(getReg().isPhysical() &&
"isRenamable should only be checked on physical registers");
if (!IsRenamable)
return false;
void MachineOperand::setIsRenamable(bool Val) {
assert(isReg() && "Wrong MachineOperand accessor");
- assert(Register::isPhysicalRegister(getReg()) &&
+ assert(getReg().isPhysical() &&
"setIsRenamable should only be called on physical registers");
IsRenamable = Val;
}
OS << "undef ";
if (isEarlyClobber())
OS << "early-clobber ";
- if (Register::isPhysicalRegister(getReg()) && isRenamable())
+ if (getReg().isPhysical() && isRenamable())
OS << "renamable ";
// isDebug() is exactly true for register operands of a DBG_VALUE. So we
// simply infer it when parsing and do not need to print it.
const MachineRegisterInfo *MRI = nullptr;
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
if (const MachineFunction *MF = getMFIfAvailable(*this)) {
MRI = &MF->getRegInfo();
}
OS << ".subreg" << SubReg;
}
// Print the register class / bank.
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
if (const MachineFunction *MF = getMFIfAvailable(*this)) {
const MachineRegisterInfo &MRI = MF->getRegInfo();
if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
for (const MachineOperand &MO : MI->operands())
if (MO.isReg() && MO.isUse()) {
Register Reg = MO.getReg();
- if (Register::isVirtualRegister(Reg))
+ if (Reg.isVirtual())
Uses.insert(Reg);
else if (MRI.isAllocatable(Reg))
for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
for (const MachineOperand &MO : SU->getInstr()->operands())
if (MO.isReg() && MO.isDef() && !MO.isDead()) {
Register Reg = MO.getReg();
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
if (!Uses.count(Reg))
LiveOutRegs.push_back(RegisterMaskPair(Reg,
LaneBitmask::getNone()));
for (std::deque<SUnit *>::iterator I = Insts.begin(), E = Insts.end(); I != E;
++I, ++Pos) {
for (MachineOperand &MO : MI->operands()) {
- if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
+ if (!MO.isReg() || !MO.getReg().isVirtual())
continue;
Register Reg = MO.getReg();
// TODO: This could be more efficient by bulk changing the operands.
for (MachineOperand &O : llvm::make_early_inc_range(reg_operands(FromReg))) {
- if (Register::isPhysicalRegister(ToReg)) {
+ if (ToReg.isPhysical()) {
O.substPhysReg(ToReg, *TRI);
} else {
O.setReg(ToReg);
LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(Register Reg) const {
// Lane masks are only defined for vregs.
- assert(Register::isVirtualRegister(Reg));
+ assert(Reg.isVirtual());
const TargetRegisterClass &TRC = *getRegClass(Reg);
return TRC.getLaneMask();
}
continue;
Register Reg = MO.getReg();
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
continue;
// Ignore re-defs.
for (const RegisterMaskPair &P : LiveUses) {
Register Reg = P.RegUnit;
/// FIXME: Currently assuming single-use physregs.
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
continue;
if (ShouldTrackLaneMasks) {
// Visit each live out vreg def to find def/use pairs that cross iterations.
for (const RegisterMaskPair &P : RPTracker.getPressure().LiveOutRegs) {
Register Reg = P.RegUnit;
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
continue;
const LiveInterval &LI = LIS->getInterval(Reg);
const VNInfo *DefVNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
// Check for pure vreg copies.
const MachineOperand &SrcOp = Copy->getOperand(1);
Register SrcReg = SrcOp.getReg();
- if (!Register::isVirtualRegister(SrcReg) || !SrcOp.readsReg())
+ if (!SrcReg.isVirtual() || !SrcOp.readsReg())
return;
const MachineOperand &DstOp = Copy->getOperand(0);
Register DstReg = DstOp.getReg();
- if (!Register::isVirtualRegister(DstReg) || DstOp.isDead())
+ if (!DstReg.isVirtual() || DstOp.isDead())
return;
// Check if either the dest or source is local. If it's live across a back
unsigned UnscheduledOper = isTop ? 0 : 1;
// If we have already scheduled the physreg produce/consumer, immediately
// schedule the copy.
- if (Register::isPhysicalRegister(MI->getOperand(ScheduledOper).getReg()))
+ if (MI->getOperand(ScheduledOper).getReg().isPhysical())
return 1;
// If the physreg is at the boundary, defer it. Otherwise schedule it
// immediately to free the dependent. We can hoist the copy later.
bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft;
- if (Register::isPhysicalRegister(MI->getOperand(UnscheduledOper).getReg()))
+ if (MI->getOperand(UnscheduledOper).getReg().isPhysical())
return AtBoundary ? -1 : 1;
}
// physical registers.
bool DoBias = true;
for (const MachineOperand &Op : MI->defs()) {
- if (Op.isReg() && !Register::isPhysicalRegister(Op.getReg())) {
+ if (Op.isReg() && !Op.getReg().isPhysical()) {
DoBias = false;
break;
}
Register SrcReg = MI.getOperand(1).getReg();
Register DstReg = MI.getOperand(0).getReg();
- if (!Register::isVirtualRegister(SrcReg) ||
- !Register::isVirtualRegister(DstReg) || !MRI->hasOneNonDBGUse(SrcReg))
+ if (!SrcReg.isVirtual() || !DstReg.isVirtual() ||
+ !MRI->hasOneNonDBGUse(SrcReg))
return false;
const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
MachineBasicBlock *DefMBB,
bool &BreakPHIEdge,
bool &LocalUse) const {
- assert(Register::isVirtualRegister(Reg) && "Only makes sense for vregs");
+ assert(Reg.isVirtual() && "Only makes sense for vregs");
// Ignore debug uses because debug info doesn't affect the code.
if (MRI->use_nodbg_empty(Reg))
// We don't move live definitions of physical registers,
// so sinking their uses won't enable any opportunities.
- if (Register::isPhysicalRegister(Reg))
+ if (Reg.isPhysical())
continue;
// If this instruction is the only user of a virtual register,
if (Reg == 0)
continue;
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
if (MO.isUse() &&
(MRI->isConstantPhysReg(Reg) || TII->isIgnorableUse(MO)))
continue;
Register Reg = MO.getReg();
if (Reg == 0) continue;
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
if (MO.isUse()) {
// If the physreg has no defs anywhere, it's just an ambient register
// and we can freely move its uses. Alternatively, if it's allocatable,
if (!Reg)
continue;
if (MO.isUse()) {
- if (Register::isPhysicalRegister(Reg) &&
+ if (Reg.isPhysical() &&
(TII->isIgnorableUse(MO) || (MRI && MRI->isConstantPhysReg(Reg))))
continue;
if (PI->modifiesRegister(Reg, TRI))
if (!MO.isReg() || MO.isUse())
continue;
Register Reg = MO.getReg();
- if (Reg == 0 || !Register::isPhysicalRegister(Reg))
+ if (Reg == 0 || !Reg.isPhysical())
continue;
if (SuccToSinkTo->isLiveIn(Reg))
return false;
SmallDenseMap<MCRegister, SmallVector<unsigned, 2>, 4> MIUnits;
bool IsValid = true;
for (MachineOperand &MO : MI.debug_operands()) {
- if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) {
+ if (MO.isReg() && MO.getReg().isPhysical()) {
// Bail if we can already tell the sink would be rejected, rather
// than needlessly accumulating lots of DBG_VALUEs.
if (hasRegisterDependency(&MI, UsedOpsInCopy, DefedRegsInCopy,
stable_hash llvm::stableHashValue(const MachineOperand &MO) {
switch (MO.getType()) {
case MachineOperand::MO_Register:
- if (Register::isVirtualRegister(MO.getReg())) {
+ if (MO.getReg().isVirtual()) {
const MachineRegisterInfo &MRI = MO.getParent()->getMF()->getRegInfo();
SmallVector<unsigned> DefOpcodes;
for (auto &Def : MRI.def_instructions(MO.getReg()))
HashComponents.push_back(MI.getOpcode());
HashComponents.push_back(MI.getFlags());
for (const MachineOperand &MO : MI.operands()) {
- if (!HashVRegs && MO.isReg() && MO.isDef() &&
- Register::isVirtualRegister(MO.getReg()))
+ if (!HashVRegs && MO.isReg() && MO.isDef() && MO.getReg().isVirtual())
continue; // Skip virtual register defs.
if (MO.isCPI()) {
Register Reg = MO.getReg();
if (!Reg)
continue;
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
HasPhysRegs = true;
continue;
}
if (!MO.isReg())
continue;
Register Reg = MO.getReg();
- if (!Register::isPhysicalRegister(Reg))
+ if (!Reg.isPhysical())
continue;
if (MO.readsReg())
ReadOps.push_back(MI.getOperandNo(MOI));
ArrayRef<const MachineBasicBlock*> Trace) {
assert(!Trace.empty() && "Trace should contain at least one block");
Register Reg = DefMI->getOperand(DefOp).getReg();
- assert(Register::isVirtualRegister(Reg));
+ assert(Reg.isVirtual());
const MachineBasicBlock *DefMBB = DefMI->getParent();
// Reg is live-in to all blocks in Trace that follow DefMBB.
}
void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const {
- if (Register::isVirtualRegister(VRegOrUnit)) {
+ if (VRegOrUnit.isVirtual()) {
report_context_vreg(VRegOrUnit);
} else {
errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
// Generic opcodes must not have physical register operands.
for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
const MachineOperand *MO = &MI->getOperand(I);
- if (MO->isReg() && Register::isPhysicalRegister(MO->getReg()))
+ if (MO->isReg() && MO->getReg().isPhysical())
report("Generic instruction cannot have physical register", MO, I);
}
report("Operand should be tied", MO, MONum);
else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
report("Tied def doesn't match MCInstrDesc", MO, MONum);
- else if (Register::isPhysicalRegister(MO->getReg())) {
+ else if (MO->getReg().isPhysical()) {
const MachineOperand &MOTied = MI->getOperand(TiedTo);
if (!MOTied.isReg())
report("Tied counterpart must be a register", &MOTied, TiedTo);
- else if (Register::isPhysicalRegister(MOTied.getReg()) &&
+ else if (MOTied.getReg().isPhysical() &&
MO->getReg() != MOTied.getReg())
report("Tied physical registers must match.", &MOTied, TiedTo);
}
// Check register classes.
unsigned SubIdx = MO->getSubReg();
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
if (SubIdx) {
report("Illegal subregister index for physical register", MO, MONum);
return;
if (MO->isDead()) {
LiveQueryResult LRQ = LR.Query(DefIdx);
if (!LRQ.isDeadDef()) {
- assert(Register::isVirtualRegister(VRegOrUnit) &&
- "Expecting a virtual register.");
+ assert(VRegOrUnit.isVirtual() && "Expecting a virtual register.");
// A dead subreg def only tells us that the specific subreg is dead. There
// could be other non-dead defs of other subregs, or we could have other
// parts of the register being live through the instruction. So unless we
MODef.isEarlyClobber() || MODef.isDebug())
report("Unexpected flag on PHI operand", &MODef, 0);
Register DefReg = MODef.getReg();
- if (!Register::isVirtualRegister(DefReg))
+ if (!DefReg.isVirtual())
report("Expected first PHI operand to be a virtual register", &MODef, 0);
for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
if (!MOI->isReg() || !MOI->isDef())
continue;
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
if (MOI->getReg() != Reg)
continue;
} else {
- if (!Register::isPhysicalRegister(MOI->getReg()) ||
- !TRI->hasRegUnit(MOI->getReg(), Reg))
+ if (!MOI->getReg().isPhysical() || !TRI->hasRegUnit(MOI->getReg(), Reg))
continue;
}
if (LaneMask.any() &&
return;
// RegUnit intervals are allowed dead phis.
- if (!Register::isVirtualRegister(Reg) && VNI->isPHIDef() &&
- S.start == VNI->def && S.end == VNI->def.getDeadSlot())
+ if (!Reg.isVirtual() && VNI->isPHIDef() && S.start == VNI->def &&
+ S.end == VNI->def.getDeadSlot())
return;
// The live segment is ending inside EndMBB
// The following checks only apply to virtual registers. Physreg liveness
// is too weird to check.
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
// A live segment can end with either a redefinition, a kill flag on a
// use, or a dead flag on a def.
bool hasRead = false;
while (true) {
assert(LiveInts->isLiveInToMBB(LR, &*MFI));
// We don't know how to track physregs into a landing pad.
- if (!Register::isVirtualRegister(Reg) && MFI->isEHPad()) {
+ if (!Reg.isVirtual() && MFI->isEHPad()) {
if (&*MFI == EndMBB)
break;
++MFI;
void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
Register Reg = LI.reg();
- assert(Register::isVirtualRegister(Reg));
+ assert(Reg.isVirtual());
verifyLiveRange(LI, Reg);
LaneBitmask Mask;
BBI != BBE; ++BBI) {
for (unsigned i = 0, e = BBI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = BBI->getOperand(i);
- if (!MO.isReg() || !MO.isDef() ||
- !Register::isVirtualRegister(MO.getReg()))
+ if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
continue;
int StageScheduled = Schedule.getStage(&*BBI);
continue;
Register reg = MO.getReg();
// Assume physical registers are used, unless they are marked dead.
- if (Register::isPhysicalRegister(reg)) {
+ if (reg.isPhysical()) {
used = !MO.isDead();
if (used)
break;
unsigned InstrStageNum,
ValueMapTy *VRMap) {
for (MachineOperand &MO : NewMI->operands()) {
- if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
+ if (!MO.isReg() || !MO.getReg().isVirtual())
continue;
Register reg = MO.getReg();
if (MO.isDef()) {
// Skip over register-to-register moves.
if (SrcMI && SrcMI->isCopy() && !SrcMI->getOperand(0).getSubReg() &&
!SrcMI->getOperand(1).getSubReg() &&
- Register::isVirtualRegister(SrcMI->getOperand(1).getReg())) {
+ SrcMI->getOperand(1).getReg().isVirtual()) {
SrcReg = SrcMI->getOperand(1).getReg();
SrcMI = MRI->getVRegDef(SrcReg);
}
bool OptimizePHIs::IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle) {
assert(MI->isPHI() && "IsDeadPHICycle expects a PHI instruction");
Register DstReg = MI->getOperand(0).getReg();
- assert(Register::isVirtualRegister(DstReg) &&
- "PHI destination is not a virtual register");
+ assert(DstReg.isVirtual() && "PHI destination is not a virtual register");
// See if we already saw this register.
if (!PHIsInCycle.insert(MI).second)
unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
isImplicitlyDefined(SrcReg, *MRI);
- assert(Register::isVirtualRegister(SrcReg) &&
+ assert(SrcReg.isVirtual() &&
"Machine PHI Operands must all be virtual registers!");
// Get the MachineBasicBlock equivalent of the BasicBlock that is the source
do {
CurSrcPair = SrcToLook.pop_back_val();
// As explained above, do not handle physical registers
- if (Register::isPhysicalRegister(CurSrcPair.Reg))
+ if (CurSrcPair.Reg.isPhysical())
return false;
ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, TII);
// constraints to the register allocator. Moreover, if we want to extend
// the live-range of a physical register, unlike SSA virtual register,
// we will have to check that they aren't redefine before the related use.
- if (Register::isPhysicalRegister(CurSrcPair.Reg))
+ if (CurSrcPair.Reg.isPhysical())
return false;
// Keep following the chain if the value isn't any better yet.
"Coalescer can understand multiple defs?!");
const MachineOperand &MODef = MI.getOperand(0);
// Do not rewrite physical definitions.
- if (Register::isPhysicalRegister(MODef.getReg()))
+ if (MODef.getReg().isPhysical())
return false;
bool Changed = false;
MachineInstr &
PeepholeOptimizer::rewriteSource(MachineInstr &CopyLike,
RegSubRegPair Def, RewriteMapTy &RewriteMap) {
- assert(!Register::isPhysicalRegister(Def.Reg) &&
- "We do not rewrite physical registers");
+ assert(!Def.Reg.isPhysical() && "We do not rewrite physical registers");
// Find the new source to use in the COPY rewrite.
RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap);
while (CpyRewriter.getNextRewritableSource(Src, Def)) {
// If a physical register is here, this is probably for a good reason.
// Do not rewrite that.
- if (Register::isPhysicalRegister(Def.Reg))
+ if (Def.Reg.isPhysical())
return false;
// If we do not know how to rewrite this definition, there is no point
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
- if (isNAPhysCopy(SrcReg) && Register::isVirtualRegister(DstReg)) {
+ if (isNAPhysCopy(SrcReg) && DstReg.isVirtual()) {
// %vreg = COPY $physreg
// Avoid using a datastructure which can track multiple live non-allocatable
// phys->virt copies since LLVM doesn't seem to do this.
// If we can still move up in the use-def chain, move to the next
// definition.
- if (!Register::isPhysicalRegister(Reg) && OneRegSrc) {
+ if (!Reg.isPhysical() && OneRegSrc) {
MachineRegisterInfo::def_iterator DI = MRI.def_begin(Reg);
if (DI != MRI.def_end()) {
Def = DI->getParent();
LLVM_DEBUG(dbgs() << "Processing " << *MI);
Register Reg = MI->getOperand(0).getReg();
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
// For virtual registers, mark all uses as <undef>, and convert users to
// implicit-def when possible.
for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
if (!MO.isReg())
continue;
Register UserReg = MO.getReg();
- if (!Register::isPhysicalRegister(UserReg) ||
- !TRI->regsOverlap(Reg, UserReg))
+ if (!UserReg.isPhysical() || !TRI->regsOverlap(Reg, UserReg))
continue;
// UserMI uses or redefines Reg. Set <undef> flags on all uses.
Found = true;
if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
continue;
Register R = Op.getReg();
- if (!R || !Register::isPhysicalRegister(R))
+ if (!R || !R.isPhysical())
continue;
uint16_t Flags = NodeAttrs::None;
if (TOI.isPreserving(In, OpN)) {
if (!Op.isReg() || !Op.isDef() || !Op.isImplicit())
continue;
Register R = Op.getReg();
- if (!R || !Register::isPhysicalRegister(R) || DoneDefs.test(R))
+ if (!R || !R.isPhysical() || DoneDefs.test(R))
continue;
RegisterRef RR = makeRegRef(Op);
uint16_t Flags = NodeAttrs::None;
if (!Op.isReg() || !Op.isUse())
continue;
Register R = Op.getReg();
- if (!R || !Register::isPhysicalRegister(R))
+ if (!R || !R.isPhysical())
continue;
uint16_t Flags = NodeAttrs::None;
if (Op.isUndef())
if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
continue;
Register R = Op.getReg();
- if (!Register::isPhysicalRegister(R))
+ if (!R.isPhysical())
continue;
for (MCSubRegIterator SR(R, &TRI, true); SR.isValid(); ++SR)
Live.reset(*SR);
if (!Op.isReg() || !Op.isUse() || Op.isUndef())
continue;
Register R = Op.getReg();
- if (!Register::isPhysicalRegister(R))
+ if (!R.isPhysical())
continue;
bool IsLive = false;
for (MCRegAliasIterator AR(R, &TRI, true); AR.isValid(); ++AR) {
continue;
}
LLVM_DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
- assert(Register::isVirtualRegister(SplitVirtReg->reg()) &&
+ assert(SplitVirtReg->reg().isVirtual() &&
"expect split value in virtual register");
enqueue(SplitVirtReg);
++NumNewQueued;
// Check if any interfering live range is heavier than MaxWeight.
for (const LiveInterval *Intf : reverse(Interferences)) {
- assert(Register::isVirtualRegister(Intf->reg()) &&
+ assert(Intf->reg().isVirtual() &&
"Only expecting virtual register interference from query");
// Do not allow eviction of a virtual register if we are in the middle
false)
bool RegAllocFast::shouldAllocateRegister(const Register Reg) const {
- assert(Register::isVirtualRegister(Reg));
+ assert(Reg.isVirtual());
const TargetRegisterClass &RC = *MRI->getRegClass(Reg);
return ShouldAllocateClass(*TRI, RC);
}
void RegAllocFast::allocVirtRegUndef(MachineOperand &MO) {
assert(MO.isUndef() && "expected undef use");
Register VirtReg = MO.getReg();
- assert(Register::isVirtualRegister(VirtReg) && "Expected virtreg");
+ assert(VirtReg.isVirtual() && "Expected virtreg");
if (!shouldAllocateRegister(VirtReg))
return;
// Ignore DBG_VALUEs that aren't based on virtual registers. These are
// mostly constants and frame indices.
for (Register Reg : MI.getUsedDebugRegs()) {
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
continue;
if (!shouldAllocateRegister(Reg))
continue;
Reg = RecoloringCandidates.pop_back_val();
// We cannot recolor physical register.
- if (Register::isPhysicalRegister(Reg))
+ if (Reg.isPhysical())
continue;
// This may be a skipped class
/// getting rid of 2 copies.
void RAGreedy::tryHintsRecoloring() {
for (const LiveInterval *LI : SetOfBrokenHints) {
- assert(Register::isVirtualRegister(LI->reg()) &&
+ assert(LI->reg().isVirtual() &&
"Recoloring is possible only for virtual registers");
// Some dead defs may be around (e.g., because of debug uses).
// Ignore those.
const RegisterBank *
RegisterBankInfo::getRegBank(Register Reg, const MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI) const {
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
// FIXME: This was probably a copy to a virtual register that does have a
// type we could use.
return &getRegBankFromRegClass(getMinimalPhysRegClass(Reg, TRI), LLT());
const TargetRegisterClass &
RegisterBankInfo::getMinimalPhysRegClass(Register Reg,
const TargetRegisterInfo &TRI) const {
- assert(Register::isPhysicalRegister(Reg) && "Reg must be a physreg");
+ assert(Reg.isPhysical() && "Reg must be a physreg");
const auto &RegRCIt = PhysRegMinimalRCs.find(Reg);
if (RegRCIt != PhysRegMinimalRCs.end())
return *RegRCIt->second;
unsigned RegisterBankInfo::getSizeInBits(Register Reg,
const MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI) const {
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
// The size is not directly available for physical registers.
// Instead, we need to access a register class that contains Reg and
// get the size of that register class.
Partial = SrcSub || DstSub;
// If one register is a physreg, it must be Dst.
- if (Register::isPhysicalRegister(Src)) {
- if (Register::isPhysicalRegister(Dst))
+ if (Src.isPhysical()) {
+ if (Dst.isPhysical())
return false;
std::swap(Src, Dst);
std::swap(SrcSub, DstSub);
const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
- if (Register::isPhysicalRegister(Dst)) {
+ if (Dst.isPhysical()) {
// Eliminate DstSub on a physreg.
if (DstSub) {
Dst = TRI.getSubReg(Dst, DstSub);
CrossClass = NewRC != DstRC || NewRC != SrcRC;
}
// Check our invariants
- assert(Register::isVirtualRegister(Src) && "Src must be virtual");
- assert(!(Register::isPhysicalRegister(Dst) && DstSub) &&
- "Cannot have a physical SubIdx");
+ assert(Src.isVirtual() && "Src must be virtual");
+ assert(!(Dst.isPhysical() && DstSub) && "Cannot have a physical SubIdx");
SrcReg = Src;
DstReg = Dst;
return true;
}
bool CoalescerPair::flip() {
- if (Register::isPhysicalRegister(DstReg))
+ if (DstReg.isPhysical())
return false;
std::swap(SrcReg, DstReg);
std::swap(SrcIdx, DstIdx);
TII->commuteInstruction(*DefMI, false, UseOpIdx, NewDstIdx);
if (!NewMI)
return { false, false };
- if (Register::isVirtualRegister(IntA.reg()) &&
- Register::isVirtualRegister(IntB.reg()) &&
+ if (IntA.reg().isVirtual() && IntB.reg().isVirtual() &&
!MRI->constrainRegClass(IntB.reg(), MRI->getRegClass(IntA.reg())))
return { false, false };
if (NewMI != DefMI) {
continue;
// Kill flags are no longer accurate. They are recomputed after RA.
UseMO.setIsKill(false);
- if (Register::isPhysicalRegister(NewReg))
+ if (NewReg.isPhysical())
UseMO.substPhysReg(NewReg, *TRI);
else
UseMO.setReg(NewReg);
unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx();
Register DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx();
- if (Register::isPhysicalRegister(SrcReg))
+ if (SrcReg.isPhysical())
return false;
LiveInterval &SrcInt = LIS->getInterval(SrcReg);
} else {
// Theoretically, some stack frame reference could exist. Just make sure
// it hasn't actually happened.
- assert(Register::isVirtualRegister(DstReg) &&
+ assert(DstReg.isVirtual() &&
"Only expect to deal with virtual or physical registers");
}
}
if (MO.isReg()) {
assert(MO.isImplicit() && "No explicit operands after implicit operands.");
// Discard VReg implicit defs.
- if (Register::isPhysicalRegister(MO.getReg()))
+ if (MO.getReg().isPhysical())
ImplicitOps.push_back(MO);
}
}
i != e; ++i) {
MachineOperand &MO = NewMI.getOperand(i);
if (MO.isReg() && MO.isDef()) {
- assert(MO.isImplicit() && MO.isDead() &&
- Register::isPhysicalRegister(MO.getReg()));
+ assert(MO.isImplicit() && MO.isDead() && MO.getReg().isPhysical());
NewMIImplDefs.push_back(MO.getReg().asMCReg());
}
}
} else if (NewMI.getOperand(0).getReg() != CopyDstReg) {
// The New instruction may be defining a sub-register of what's actually
// been asked for. If so it must implicitly define the whole thing.
- assert(Register::isPhysicalRegister(DstReg) &&
+ assert(DstReg.isPhysical() &&
"Only expect virtual or physical registers in remat");
NewMI.getOperand(0).setIsDead(true);
NewMI.addOperand(MachineOperand::CreateReg(
llvm::make_early_inc_range(MRI->use_operands(SrcReg))) {
MachineInstr *UseMI = UseMO.getParent();
if (UseMI->isDebugInstr()) {
- if (Register::isPhysicalRegister(DstReg))
+ if (DstReg.isPhysical())
UseMO.substPhysReg(DstReg, *TRI);
else
UseMO.setReg(DstReg);
void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg,
unsigned SubIdx) {
- bool DstIsPhys = Register::isPhysicalRegister(DstReg);
+ bool DstIsPhys = DstReg.isPhysical();
LiveInterval *DstInt = DstIsPhys ? nullptr : &LIS->getInterval(DstReg);
if (DstInt && DstInt->hasSubRanges() && DstReg != SrcReg) {
assert(MI && "No instruction to erase");
if (MI->isCopy()) {
Register Reg = MI->getOperand(1).getReg();
- if (Register::isVirtualRegister(Reg) && Reg != CP.getSrcReg() &&
- Reg != CP.getDstReg())
+ if (Reg.isVirtual() && Reg != CP.getSrcReg() && Reg != CP.getDstReg())
ShrinkRegs.push_back(Reg);
}
ErasedInstrs.insert(MI);
Register SrcReg = Copy->getOperand(1).getReg();
Register DstReg = Copy->getOperand(0).getReg();
- if (Register::isPhysicalRegister(SrcReg) ||
- Register::isPhysicalRegister(DstReg))
+ if (SrcReg.isPhysical() || DstReg.isPhysical())
return false;
return LIS->intervalIsInOneMBB(LIS->getInterval(SrcReg))
if (OtherReg == SrcReg)
OtherReg = OtherSrcReg;
// Check if OtherReg is a non-terminal.
- if (Register::isPhysicalRegister(OtherReg) ||
- isTerminalReg(OtherReg, MI, MRI))
+ if (OtherReg.isPhysical() || isTerminalReg(OtherReg, MI, MRI))
continue;
// Check that OtherReg interfere with DstReg.
if (LIS->getInterval(OtherReg).overlaps(DstLI)) {
assert(isBottomClosed() && "need bottom-up tracking to intialize.");
for (const RegisterMaskPair &Pair : P.LiveOutRegs) {
Register RegUnit = Pair.RegUnit;
- if (Register::isVirtualRegister(RegUnit)
- && !RPTracker.hasUntiedDef(RegUnit))
+ if (RegUnit.isVirtual() && !RPTracker.hasUntiedDef(RegUnit))
increaseSetPressure(LiveThruPressure, *MRI, RegUnit,
LaneBitmask::getNone(), Pair.LaneMask);
}
// If the def is all that is live after the instruction, then in case
// of a subregister def we need a read-undef flag.
Register RegUnit = I->RegUnit;
- if (Register::isVirtualRegister(RegUnit) &&
- AddFlagsMI != nullptr && (LiveAfter & ~I->LaneMask).none())
+ if (RegUnit.isVirtual() && AddFlagsMI != nullptr &&
+ (LiveAfter & ~I->LaneMask).none())
AddFlagsMI->setRegisterDefReadUndef(RegUnit);
LaneBitmask ActualDef = I->LaneMask & LiveAfter;
if (AddFlagsMI != nullptr) {
for (const RegisterMaskPair &P : DeadDefs) {
Register RegUnit = P.RegUnit;
- if (!Register::isVirtualRegister(RegUnit))
+ if (!RegUnit.isVirtual())
continue;
LaneBitmask LiveAfter = getLiveLanesAt(LIS, MRI, true, RegUnit,
Pos.getDeadSlot());
if (TrackUntiedDefs) {
for (const RegisterMaskPair &Def : RegOpers.Defs) {
Register RegUnit = Def.RegUnit;
- if (Register::isVirtualRegister(RegUnit) &&
+ if (RegUnit.isVirtual() &&
(LiveRegs.contains(RegUnit) & Def.LaneMask).none())
UntiedDefs.insert(RegUnit);
}
if (!MO.isReg())
continue;
Register Reg = MO.getReg();
- if (!Register::isPhysicalRegister(Reg) || isReserved(Reg))
+ if (!Reg.isPhysical() || isReserved(Reg))
continue;
if (MO.isUse()) {
if (MO.isUndef())
Candidates.clearBitsNotInMask(MO.getRegMask());
if (!MO.isReg() || MO.isUndef() || !MO.getReg())
continue;
- if (Register::isVirtualRegister(MO.getReg())) {
+ if (MO.getReg().isVirtual()) {
if (MO.isDef())
isVirtDefInsn = true;
else if (MO.isKill())
// be usefull for this other vreg as well later.
bool FoundVReg = false;
for (const MachineOperand &MO : MI.operands()) {
- if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
+ if (MO.isReg() && MO.getReg().isVirtual()) {
FoundVReg = true;
break;
}
// Exclude all the registers being used by the instruction.
for (const MachineOperand &MO : MI.operands()) {
if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
- !Register::isVirtualRegister(MO.getReg()))
+ !MO.getReg().isVirtual())
for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
Candidates.reset(*AI);
}
// We only care about virtual registers and ignore virtual registers
// created by the target callbacks in the process (those will be handled
// in a scavenging round).
- if (!Register::isVirtualRegister(Reg) ||
+ if (!Reg.isVirtual() ||
Register::virtReg2Index(Reg) >= InitialNumVirtRegs)
continue;
if (!MO.readsReg())
continue;
Register Reg = MO.getReg();
// Only vregs, no newly created vregs (see above).
- if (!Register::isVirtualRegister(Reg) ||
+ if (!Reg.isVirtual() ||
Register::virtReg2Index(Reg) >= InitialNumVirtRegs)
continue;
// We have to look at all operands anyway so we can precalculate here
}
#ifndef NDEBUG
for (const MachineOperand &MO : MBB.front().operands()) {
- if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
+ if (!MO.isReg() || !MO.getReg().isVirtual())
continue;
assert(!MO.isInternalRead() && "Cannot assign inside bundles");
assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses");
for (const MachineOperand &MO : ExitMI->operands()) {
if (!MO.isReg() || MO.isDef()) continue;
Register Reg = MO.getReg();
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
- } else if (Register::isVirtualRegister(Reg) && MO.readsReg()) {
+ } else if (Reg.isVirtual() && MO.readsReg()) {
addVRegUseDeps(&ExitSU, ExitMI->getOperandNo(&MO));
}
}
if (!MO.isReg() || !MO.isDef())
continue;
Register Reg = MO.getReg();
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
addPhysRegDeps(SU, j);
- } else if (Register::isVirtualRegister(Reg)) {
+ } else if (Reg.isVirtual()) {
HasVRegDef = true;
addVRegDefDeps(SU, j);
}
if (!MO.isReg() || !MO.isUse())
continue;
Register Reg = MO.getReg();
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
addPhysRegDeps(SU, j);
- } else if (Register::isVirtualRegister(Reg) && MO.readsReg()) {
+ } else if (Reg.isVirtual() && MO.readsReg()) {
addVRegUseDeps(SU, j);
}
}
Register DestReg = It->second;
if (DestReg == 0)
return;
- assert(Register::isVirtualRegister(DestReg) && "Expected a virtual reg");
+ assert(DestReg.isVirtual() && "Expected a virtual reg");
LiveOutRegInfo.grow(DestReg);
LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
"CopyToReg node was created.");
Register SrcReg = ValueMap[V];
- if (!Register::isVirtualRegister(SrcReg)) {
+ if (!SrcReg.isVirtual()) {
DestLOI.IsValid = false;
return;
}
if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
continue;
if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
- if (Register::isPhysicalRegister(RN->getReg()))
+ if (RN->getReg().isPhysical())
continue;
NumImpUses = N - I;
break;
if (User->getOpcode() == ISD::CopyToReg &&
User->getOperand(2).getNode() == Node &&
User->getOperand(2).getResNo() == i) {
- unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
- if (Register::isVirtualRegister(Reg)) {
+ Register Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
+ if (Reg.isVirtual()) {
const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
if (RegRC == RC) {
VRBase = Reg;
(IIRC && TRI->isDivergentRegClass(IIRC)))
: nullptr;
- if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) {
+ if (OpRC && IIRC && OpRC != IIRC && VReg.isVirtual()) {
Register NewVReg = MRI->createVirtualRegister(IIRC);
BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
Register Reg;
MachineInstr *DefMI;
RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
- if (R && Register::isPhysicalRegister(R->getReg())) {
+ if (R && R->getReg().isPhysical()) {
Reg = R->getReg();
DefMI = nullptr;
} else {
RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
// Skip physical registers as they don't have a vreg to get and we'll
// insert copies for them in TwoAddressInstructionPass anyway.
- if (!R || !Register::isPhysicalRegister(R->getReg())) {
+ if (!R || !R->getReg().isPhysical()) {
unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
case ISD::CopyToReg: {
Register DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
SDValue SrcVal = Node->getOperand(2);
- if (Register::isVirtualRegister(DestReg) && SrcVal.isMachineOpcode() &&
+ if (DestReg.isVirtual() && SrcVal.isMachineOpcode() &&
SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
// Instead building a COPY to that vreg destination, build an
// IMPLICIT_DEF instruction instead.
default: llvm_unreachable("Bad flags!");
case InlineAsm::Kind_RegDef:
for (unsigned j = 0; j != NumVals; ++j, ++i) {
- unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
+ Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
// FIXME: Add dead flags for physical and virtual registers defined.
// For now, mark physical register defs as implicit to help fast
// regalloc. This makes inline asm look a lot like calls.
- MIB.addReg(Reg,
- RegState::Define |
- getImplRegState(Register::isPhysicalRegister(Reg)));
+ MIB.addReg(Reg, RegState::Define | getImplRegState(Reg.isPhysical()));
}
break;
case InlineAsm::Kind_RegDefEarlyClobber:
case InlineAsm::Kind_Clobber:
for (unsigned j = 0; j != NumVals; ++j, ++i) {
- unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MIB.addReg(Reg,
- RegState::Define | RegState::EarlyClobber |
- getImplRegState(Register::isPhysicalRegister(Reg)));
+ Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
+ MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
+ getImplRegState(Reg.isPhysical()));
ECRegs.push_back(Reg);
}
break;
// Check for def of register or earlyclobber register.
for (; NumVals; --NumVals, ++i) {
Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- if (Register::isPhysicalRegister(Reg))
+ if (Reg.isPhysical())
CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
}
} else
PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {
Register Reg =
cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
RetVal = true;
continue;
}
if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) {
Register Reg =
cast<RegisterSDNode>(SuccSU->getNode()->getOperand(1))->getReg();
- if (Register::isVirtualRegister(Reg)) {
+ if (Reg.isVirtual()) {
RetVal = true;
continue;
}
// like other nodes from the perspective of scheduling heuristics.
if (SDNode *N = SU.getNode())
if (N->getOpcode() == ISD::CopyToReg &&
- Register::isVirtualRegister(
- cast<RegisterSDNode>(N->getOperand(1))->getReg()))
+ cast<RegisterSDNode>(N->getOperand(1))->getReg().isVirtual())
continue;
SDNode *PredFrameSetup = nullptr;
// like other nodes from the perspective of scheduling heuristics.
if (SDNode *N = SU.getNode())
if (N->getOpcode() == ISD::CopyFromReg &&
- Register::isVirtualRegister(
- cast<RegisterSDNode>(N->getOperand(1))->getReg()))
+ cast<RegisterSDNode>(N->getOperand(1))->getReg().isVirtual())
continue;
// Perform checks on the successors of PredSU.
To = J->second;
}
// Make sure the new register has a sufficiently constrained register class.
- if (Register::isVirtualRegister(From) && Register::isVirtualRegister(To))
+ if (From.isVirtual() && To.isVirtual())
MRI.constrainRegClass(To, MRI.getRegClass(From));
// Replace it.
bool hasFI = MI->getDebugOperand(0).isFI();
Register Reg =
hasFI ? TRI.getFrameRegister(*MF) : MI->getDebugOperand(0).getReg();
- if (Register::isPhysicalRegister(Reg))
+ if (Reg.isPhysical())
EntryMBB->insert(EntryMBB->begin(), MI);
else {
MachineInstr *Def = RegInfo->getVRegDef(Reg);
Register PhysReg = MO.getReg();
if (!PhysReg)
continue;
- assert(Register::isPhysicalRegister(PhysReg) && "Unallocated register?!");
+ assert(PhysReg.isPhysical() && "Unallocated register?!");
// The stack pointer is not normally described as a callee-saved register
// in calling convention definitions, so we need to watch for it
// separately. An SP mentioned by a call instruction, we can ignore,
return ++MOI;
}
- assert(Register::isPhysicalRegister(MOI->getReg()) &&
+ assert(MOI->getReg().isPhysical() &&
"Virtreg operands should have been rewritten before now.");
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg());
assert(!MOI->getSubReg() && "Physical subreg still around.");
if (!MO.isReg())
continue;
Register Reg = MO.getReg();
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
continue;
if (MO.isDef()) {
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
bool Reg2IsInternal = MI.getOperand(Idx2).isInternalRead();
// Avoid calling isRenamable for virtual registers since we assert that
// renamable property is only queried/set for physical registers.
- bool Reg1IsRenamable = Register::isPhysicalRegister(Reg1)
- ? MI.getOperand(Idx1).isRenamable()
- : false;
- bool Reg2IsRenamable = Register::isPhysicalRegister(Reg2)
- ? MI.getOperand(Idx2).isRenamable()
- : false;
+ bool Reg1IsRenamable =
+ Reg1.isPhysical() ? MI.getOperand(Idx1).isRenamable() : false;
+ bool Reg2IsRenamable =
+ Reg2.isPhysical() ? MI.getOperand(Idx2).isRenamable() : false;
// If destination is tied to either of the commuted source register, then
// it must be updated.
if (HasDef && Reg0 == Reg1 &&
CommutedMI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal);
// Avoid calling setIsRenamable for virtual registers since we assert that
// renamable property is only queried/set for physical registers.
- if (Register::isPhysicalRegister(Reg1))
+ if (Reg1.isPhysical())
CommutedMI->getOperand(Idx2).setIsRenamable(Reg1IsRenamable);
- if (Register::isPhysicalRegister(Reg2))
+ if (Reg2.isPhysical())
CommutedMI->getOperand(Idx1).setIsRenamable(Reg2IsRenamable);
return CommutedMI;
}
Register FoldReg = FoldOp.getReg();
Register LiveReg = LiveOp.getReg();
- assert(Register::isVirtualRegister(FoldReg) && "Cannot fold physregs");
+ assert(FoldReg.isVirtual() && "Cannot fold physregs");
const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
- if (Register::isPhysicalRegister(LiveOp.getReg()))
+ if (LiveOp.getReg().isPhysical())
return RC->contains(LiveOp.getReg()) ? RC : nullptr;
if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
// reassociate.
MachineInstr *MI1 = nullptr;
MachineInstr *MI2 = nullptr;
- if (Op1.isReg() && Register::isVirtualRegister(Op1.getReg()))
+ if (Op1.isReg() && Op1.getReg().isVirtual())
MI1 = MRI.getUniqueVRegDef(Op1.getReg());
- if (Op2.isReg() && Register::isVirtualRegister(Op2.getReg()))
+ if (Op2.isReg() && Op2.getReg().isVirtual())
MI2 = MRI.getUniqueVRegDef(Op2.getReg());
// And at least one operand must be defined in MBB.
Register RegY = OpY.getReg();
Register RegC = OpC.getReg();
- if (Register::isVirtualRegister(RegA))
+ if (RegA.isVirtual())
MRI.constrainRegClass(RegA, RC);
- if (Register::isVirtualRegister(RegB))
+ if (RegB.isVirtual())
MRI.constrainRegClass(RegB, RC);
- if (Register::isVirtualRegister(RegX))
+ if (RegX.isVirtual())
MRI.constrainRegClass(RegX, RC);
- if (Register::isVirtualRegister(RegY))
+ if (RegY.isVirtual())
MRI.constrainRegClass(RegY, RC);
- if (Register::isVirtualRegister(RegC))
+ if (RegC.isVirtual())
MRI.constrainRegClass(RegC, RC);
// Create a new virtual register for the result of (X op Y) instead of
// doesn't read the other parts of the register. Otherwise it is really a
// read-modify-write operation on the full virtual register which cannot be
// moved safely.
- if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() &&
+ if (DefReg.isVirtual() && MI.getOperand(0).getSubReg() &&
MI.readsVirtualRegister(DefReg))
return false;
continue;
// Check for a well-behaved physical register.
- if (Register::isPhysicalRegister(Reg)) {
+ if (Reg.isPhysical()) {
if (MO.isUse()) {
// If the physreg has no defs anywhere, it's just an ambient register
// and we can freely move its uses. Alternatively, if it's allocatable,
OS << "$noreg";
else if (Register::isStackSlot(Reg))
OS << "SS#" << Register::stackSlot2Index(Reg);
- else if (Register::isVirtualRegister(Reg)) {
+ else if (Reg.isVirtual()) {
StringRef Name = MRI ? MRI->getVRegName(Reg) : "";
if (Name != "") {
OS << '%' << Name;
projects / platform / upstream / llvm.git / commitdiff