Formatting

Commit migrated from https://github.com/dotnet/coreclr/commit/121da5fd07ca2034cef5e6f73d65901039cd79c6

diff --git a/src/coreclr/src/jit/codegenarm.cpp b/src/coreclr/src/jit/codegenarm.cpp
index 5892757..0795299 100644 (file)
--- a/src/coreclr/src/jit/codegenarm.cpp
+++ b/src/coreclr/src/jit/codegenarm.cpp
@@ -1221,8 +1221,8 @@ void CodeGen::genCodeForNegNot(GenTree* tree)
 
     assert(!tree->OperIs(GT_NOT) || !varTypeIsFloating(targetType));
 
-    regNumber targetReg  = tree->gtRegNum;
-    instruction ins = genGetInsForOper(tree->OperGet(), targetType);
+    regNumber   targetReg = tree->gtRegNum;
+    instruction ins       = genGetInsForOper(tree->OperGet(), targetType);
 
     // The arithmetic node must be sitting in a register (since it's not contained)
     assert(!tree->isContained());
@@ -1333,8 +1333,7 @@ void CodeGen::genCodeForLclVar(GenTreeLclVar* tree)
     if (!tree->InReg() && !(tree->gtFlags & GTF_SPILLED))
     {
         assert(!isRegCandidate);
-        getEmitter()->emitIns_R_S(ins_Load(tree->TypeGet()), emitTypeSize(tree), tree->gtRegNum,
-                          tree->gtLclNum, 0);
+        getEmitter()->emitIns_R_S(ins_Load(tree->TypeGet()), emitTypeSize(tree), tree->gtRegNum, tree->gtLclNum, 0);
         genProduceReg(tree);
     }
 }
@@ -1519,8 +1518,8 @@ void CodeGen::genCodeForCompare(GenTreeOp* tree)
     else
     {
         regNumber targetReg = tree->gtRegNum;
-        emitter* emit = getEmitter();
-        emitAttr cmpAttr;
+        emitter*  emit      = getEmitter();
+        emitAttr  cmpAttr;
 
         genConsumeIfReg(op1);
         genConsumeIfReg(op2);
@@ -1529,7 +1528,7 @@ void CodeGen::genCodeForCompare(GenTreeOp* tree)
         {
             assert(op1->TypeGet() == op2->TypeGet());
             instruction ins = INS_vcmp;
-            cmpAttr = emitTypeSize(op1->TypeGet());
+            cmpAttr         = emitTypeSize(op1->TypeGet());
             emit->emitInsBinary(ins, cmpAttr, op1, op2);
             // vmrs with register 0xf has special meaning of transferring flags
             emit->emitIns_R(INS_vmrs, EA_4BYTE, REG_R15);

diff --git a/src/coreclr/src/jit/codegenarm64.cpp b/src/coreclr/src/jit/codegenarm64.cpp
index 4ab3df6..3e4aa4e 100644 (file)
--- a/src/coreclr/src/jit/codegenarm64.cpp
+++ b/src/coreclr/src/jit/codegenarm64.cpp
@@ -2897,8 +2897,8 @@ void CodeGen::genCodeForNegNot(GenTree* tree)
 
     assert(!tree->OperIs(GT_NOT) || !varTypeIsFloating(targetType));
 
-    regNumber targetReg  = tree->gtRegNum;
-    instruction ins = genGetInsForOper(tree->OperGet(), targetType);
+    regNumber   targetReg = tree->gtRegNum;
+    instruction ins       = genGetInsForOper(tree->OperGet(), targetType);
 
     // The arithmetic node must be sitting in a register (since it's not contained)
     assert(!tree->isContained());
@@ -4319,8 +4319,8 @@ void CodeGen::genCkfinite(GenTreePtr treeNode)
 //
 void CodeGen::genCodeForCompare(GenTreeOp* tree)
 {
-    regNumber targetReg  = tree->gtRegNum;
-    emitter*  emit       = getEmitter();
+    regNumber targetReg = tree->gtRegNum;
+    emitter*  emit      = getEmitter();
 
     // TODO-ARM64-CQ: Check if we can use the currently set flags.
     // TODO-ARM64-CQ: Check for the case where we can simply transfer the carry bit to a register

diff --git a/src/coreclr/src/jit/codegenarmarch.cpp b/src/coreclr/src/jit/codegenarmarch.cpp
index 4c9e676..a64c29b 100644 (file)
--- a/src/coreclr/src/jit/codegenarmarch.cpp
+++ b/src/coreclr/src/jit/codegenarmarch.cpp
@@ -541,7 +541,8 @@ void CodeGen::genPutArgReg(GenTreeOp* tree)
     var_types targetType = tree->TypeGet();
     regNumber targetReg  = tree->gtRegNum;
 
-    assert(targetType != TYP_STRUCT); // Any TYP_STRUCT register args should have been removed by fgMorphMultiregStructArg
+    assert(targetType !=
+           TYP_STRUCT); // Any TYP_STRUCT register args should have been removed by fgMorphMultiregStructArg
 
     // We have a normal non-Struct targetType