config M68K
bool "M68000 architecture"
+ select HAVE_PRIVATE_LIBGCC
select HAVE_GENERIC_BOARD
select SYS_GENERIC_BOARD
config TARGET_STM32F429_DISCOVERY
bool "Support STM32F429 Discovery"
select CPU_V7M
+ select DM
+ select DM_SERIAL
config ARCH_ROCKCHIP
bool "Support Rockchip SoCs"
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+
+ /* Trigger initialization */
+ writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
+ /* Wait 1ms because of L3 timeout error */
+ udelay(1000);
+
+ /* Write proper sdram_ref_cref_ctrl value */
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
}
EMIF_REG_INITREF_DIS_MASK);
#endif
if (regs->zq_config)
- writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
+ /* Set time between rising edge of DDR_RESET to rising
+ * edge of DDR_CKE to > 500us per memory spec. */
+ writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->emif_ddr_phy_ctlr_1,
&emif_reg[nr]->emif_ddr_phy_ctrl_1);
break;
case BOOT_DEVICE_MMC2:
case BOOT_DEVICE_MMC2_2:
+ omap_mmc_init(0, 0, 0, -1, -1);
omap_mmc_init(1, 0, 0, -1, -1);
break;
}
* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
*
* (C) Copyright 2015
- * Kamil Lulko, <rev13@wp.pl>
+ * Kamil Lulko, <kamil.lulko@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define STM32_FLASH_CR_SNB_OFFSET 3
#define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET)
+/*
+ * Peripheral base addresses
+ */
+#define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000)
+#define STM32_USART2_BASE (STM32_APB1PERIPH_BASE + 0x4400)
+#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800)
+#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400)
+
enum clock {
CLOCK_CORE,
CLOCK_AHB,
# SPDX-License-Identifier: GPL-2.0+
#
+## Build a couple of necessary functions into a private libgcc
+## if the user asked for it
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += lshrdi3.o muldi3.o ashldi3.o
+
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cache.o
obj-y += interrupts.o
--- /dev/null
+/*
+ * ashldi3.c extracted from gcc-2.7.2.3/libgcc2.c and
+ * gcc-2.7.2.3/longlong.h
+ *
+ * Copyright (C) 1989-2015 Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define BITS_PER_UNIT 8
+
+typedef int SItype __attribute__ ((mode (SI)));
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+typedef int DItype __attribute__ ((mode (DI)));
+typedef int word_type __attribute__ ((mode (__word__)));
+
+struct DIstruct {SItype high, low;};
+
+typedef union
+{
+ struct DIstruct s;
+ DItype ll;
+} DIunion;
+
+DItype __ashldi3 (DItype u, word_type b)
+{
+ DIunion w;
+ word_type bm;
+ DIunion uu;
+
+ if (b == 0)
+ return u;
+
+ uu.ll = u;
+
+ bm = (sizeof (SItype) * BITS_PER_UNIT) - b;
+ if (bm <= 0)
+ {
+ w.s.low = 0;
+ w.s.high = (USItype)uu.s.low << -bm;
+ }
+ else
+ {
+ USItype carries = (USItype)uu.s.low >> bm;
+ w.s.low = (USItype)uu.s.low << b;
+ w.s.high = ((USItype)uu.s.high << b) | carries;
+ }
+
+ return w.ll;
+}
\ No newline at end of file
--- /dev/null
+/*
+ * lshrdi3.c extracted from gcc-2.7.2.3/libgcc2.c and
+ * gcc-2.7.2.3/longlong.h
+ *
+ * Copyright (C) 1989-2015 Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define BITS_PER_UNIT 8
+
+typedef int SItype __attribute__ ((mode (SI)));
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+typedef int DItype __attribute__ ((mode (DI)));
+typedef int word_type __attribute__ ((mode (__word__)));
+
+struct DIstruct {SItype high, low;};
+
+typedef union
+{
+ struct DIstruct s;
+ DItype ll;
+} DIunion;
+
+DItype __lshrdi3 (DItype u, word_type b)
+{
+ DIunion w;
+ word_type bm;
+ DIunion uu;
+
+ if (b == 0)
+ return u;
+
+ uu.ll = u;
+
+ bm = (sizeof (SItype) * BITS_PER_UNIT) - b;
+ if (bm <= 0)
+ {
+ w.s.high = 0;
+ w.s.low = (USItype)uu.s.high >> -bm;
+ }
+ else
+ {
+ USItype carries = (USItype)uu.s.high << bm;
+ w.s.high = (USItype)uu.s.high >> b;
+ w.s.low = ((USItype)uu.s.low >> b) | carries;
+ }
+
+ return w.ll;
+}
\ No newline at end of file
--- /dev/null
+/*
+ * muldi3.c extracted from gcc-2.7.2.3/libgcc2.c and
+ * gcc-2.7.2.3/longlong.h
+ *
+ * Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SI_TYPE_SIZE 32
+#define __BITS4 (SI_TYPE_SIZE / 4)
+#define __ll_B (1L << (SI_TYPE_SIZE / 2))
+#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
+#define __ll_highpart(t) ((USItype) (t) / __ll_B)
+
+#define umul_ppmm(w1, w0, u, v) \
+ do { \
+ USItype __x0, __x1, __x2, __x3; \
+ USItype __ul, __vl, __uh, __vh; \
+ \
+ __ul = __ll_lowpart (u); \
+ __uh = __ll_highpart (u); \
+ __vl = __ll_lowpart (v); \
+ __vh = __ll_highpart (v); \
+ \
+ __x0 = (USItype) __ul * __vl; \
+ __x1 = (USItype) __ul * __vh; \
+ __x2 = (USItype) __uh * __vl; \
+ __x3 = (USItype) __uh * __vh; \
+ \
+ __x1 += __ll_highpart (__x0);/* this can't give carry */ \
+ __x1 += __x2; /* but this indeed can */ \
+ if (__x1 < __x2) /* did we get it? */ \
+ __x3 += __ll_B; /* yes, add it in the proper pos. */ \
+ \
+ (w1) = __x3 + __ll_highpart (__x1); \
+ (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
+ } while (0)
+
+#define __umulsidi3(u, v) \
+ ({DIunion __w; \
+ umul_ppmm (__w.s.high, __w.s.low, u, v); \
+ __w.ll; })
+
+typedef int SItype __attribute__ ((mode (SI)));
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+typedef int DItype __attribute__ ((mode (DI)));
+typedef int word_type __attribute__ ((mode (__word__)));
+
+struct DIstruct {SItype high, low;};
+
+typedef union
+{
+ struct DIstruct s;
+ DItype ll;
+} DIunion;
+
+DItype __muldi3 (DItype u, DItype v)
+{
+ DIunion w;
+ DIunion uu, vv;
+
+ uu.ll = u,
+ vv.ll = v;
+
+ w.ll = __umulsidi3 (uu.s.low, vv.s.low);
+ w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
+ + (USItype) uu.s.high * (USItype) vv.s.low);
+
+ return w.ll;
+}
config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
&draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
-
- /* For Samsung 2Gbit RAM we need this delay otherwise config fails after
- * soft reset.
- */
- udelay(2000);
}
static void spl_siemens_board_init(void)
* Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
*
* (C) Copyright 2015
- * Kamil Lulko, <rev13@wp.pl>
+ * Kamil Lulko, <kamil.lulko@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/stm32.h>
#include <asm/arch/gpio.h>
#include <asm/arch/fmc.h>
+#include <dm/platdata.h>
+#include <dm/platform_data/serial_stm32.h>
DECLARE_GLOBAL_DATA_PTR;
return rv;
}
+static const struct stm32_serial_platdata serial_platdata = {
+ .base = (struct stm32_usart *)STM32_USART1_BASE,
+};
+
+U_BOOT_DEVICE(stm32_serials) = {
+ .name = "serial_stm32",
+ .platdata = &serial_platdata,
+};
+
u32 get_board_rev(void)
{
return 0;
if (ret)
return;
+ fdt_fixup_ethernet(*of_flat_tree);
+
ret = fdt_add_subnode(*of_flat_tree, 0, "chosen");
if ((ret >= 0 || ret == -FDT_ERR_EXISTS)) {
bootline = getenv("bootargs");
char *p, *p1, *res_str = NULL;
while ((p = strchr(inp, SPECIAL_VAR_SYMBOL))) {
- /* check the beginning of the string for normal charachters */
+ /* check the beginning of the string for normal characters */
if (p != inp) {
- /* copy any charachters to the result string */
+ /* copy any characters to the result string */
len = p - inp;
res_str = xrealloc(res_str, (res_str_len + len));
strncpy((res_str + res_str_len), inp, len);
if (bootable && !info.bootable)
continue;
- sprintf(t, "%s%d", str[0] ? " " : "", p);
+ sprintf(t, "%s%x", str[0] ? " " : "", p);
strcat(str, t);
}
setenv(var, str);
unsigned long count;
u32 image_size_sectors;
struct image_header *header;
+ int dev_num = mmc->block_dev.dev;
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
sizeof(struct image_header));
/* read image header to find the image size & load address */
- count = mmc->block_dev.block_read(0, sector, 1, header);
+ count = mmc->block_dev.block_read(dev_num, sector, 1, header);
debug("read sector %lx, count=%lu\n", sector, count);
if (count == 0)
goto end;
mmc->read_bl_len;
/* Read the header too to avoid extra memcpy */
- count = mmc->block_dev.block_read(0, sector, image_size_sectors,
+ count = mmc->block_dev.block_read(dev_num, sector, image_size_sectors,
(void *)(ulong)spl_image.load_addr);
debug("read %x sectors to %x\n", image_size_sectors,
spl_image.load_addr);
{
unsigned long count;
- count = mmc->block_dev.block_read(0,
+ count = mmc->block_dev.block_read(
+ mmc->block_dev.dev,
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS,
(void *) CONFIG_SYS_SPL_ARGS_ADDR);
serial_pxa.c
serial_s3c24x0.c
serial_sa1100.c
- serial_stm32.c
serial_xuartlite.c
usbtty.c
/*
* (C) Copyright 2015
- * Kamil Lulko, <rev13@wp.pl>
+ * Kamil Lulko, <kamil.lulko@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
#include <asm/io.h>
#include <serial.h>
#include <asm/arch/stm32.h>
+#include <dm/platform_data/serial_stm32.h>
-/*
- * Set up the usart port
- */
-#if (CONFIG_STM32_USART >= 1) && (CONFIG_STM32_USART <= 6)
-#define USART_PORT (CONFIG_STM32_USART - 1)
-#else
-#define USART_PORT 0
-#endif
-/*
- * Set up the usart base address
- *
- * --STM32_USARTD_BASE means default setting
- */
-#define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000)
-#define STM32_USART2_BASE (STM32_APB1PERIPH_BASE + 0x4400)
-#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800)
-#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400)
-#define STM32_USARTD_BASE STM32_USART1_BASE
-/*
- * RCC USART specific definitions
- *
- * --RCC_ENR_USARTDEN means default setting
- */
-#define RCC_ENR_USART1EN (1 << 4)
-#define RCC_ENR_USART2EN (1 << 17)
-#define RCC_ENR_USART3EN (1 << 18)
-#define RCC_ENR_USART6EN (1 << 5)
-#define RCC_ENR_USARTDEN RCC_ENR_USART1EN
-
-struct stm32_serial {
+struct stm32_usart {
u32 sr;
u32 dr;
u32 brr;
u32 gtpr;
};
-#define USART_CR1_RE (1 << 2)
-#define USART_CR1_TE (1 << 3)
-#define USART_CR1_UE (1 << 13)
+#define USART_CR1_RE (1 << 2)
+#define USART_CR1_TE (1 << 3)
+#define USART_CR1_UE (1 << 13)
#define USART_SR_FLAG_RXNE (1 << 5)
-#define USART_SR_FLAG_TXE (1 << 7)
+#define USART_SR_FLAG_TXE (1 << 7)
-#define USART_BRR_F_MASK 0xF
+#define USART_BRR_F_MASK 0xF
#define USART_BRR_M_SHIFT 4
#define USART_BRR_M_MASK 0xFFF0
DECLARE_GLOBAL_DATA_PTR;
-static const unsigned long usart_base[] = {
- STM32_USART1_BASE,
- STM32_USART2_BASE,
- STM32_USART3_BASE,
- STM32_USARTD_BASE,
- STM32_USARTD_BASE,
- STM32_USART6_BASE
-};
+#define MAX_SERIAL_PORTS 4
-static const unsigned long rcc_enr_en[] = {
- RCC_ENR_USART1EN,
- RCC_ENR_USART2EN,
- RCC_ENR_USART3EN,
- RCC_ENR_USARTDEN,
- RCC_ENR_USARTDEN,
- RCC_ENR_USART6EN
+/*
+ * RCC USART specific definitions
+ */
+#define RCC_ENR_USART1EN (1 << 4)
+#define RCC_ENR_USART2EN (1 << 17)
+#define RCC_ENR_USART3EN (1 << 18)
+#define RCC_ENR_USART6EN (1 << 5)
+
+/* Array used to figure out which RCC bit needs to be set */
+static const unsigned long usart_port_rcc_pairs[MAX_SERIAL_PORTS][2] = {
+ { STM32_USART1_BASE, RCC_ENR_USART1EN },
+ { STM32_USART2_BASE, RCC_ENR_USART2EN },
+ { STM32_USART3_BASE, RCC_ENR_USART3EN },
+ { STM32_USART6_BASE, RCC_ENR_USART6EN }
};
-static void stm32_serial_setbrg(void)
+static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
{
- serial_init();
-}
+ struct stm32_serial_platdata *plat = dev->platdata;
+ struct stm32_usart *const usart = plat->base;
+ u32 clock, int_div, frac_div, tmp;
-static int stm32_serial_init(void)
-{
- struct stm32_serial *usart =
- (struct stm32_serial *)usart_base[USART_PORT];
- u32 clock, int_div, frac_div, tmp;
-
- if ((usart_base[USART_PORT] & STM32_BUS_MASK) ==
- STM32_APB1PERIPH_BASE) {
- setbits_le32(&STM32_RCC->apb1enr, rcc_enr_en[USART_PORT]);
+ if (((u32)usart & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE)
clock = clock_get(CLOCK_APB1);
- } else if ((usart_base[USART_PORT] & STM32_BUS_MASK) ==
- STM32_APB2PERIPH_BASE) {
- setbits_le32(&STM32_RCC->apb2enr, rcc_enr_en[USART_PORT]);
+ else if (((u32)usart & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE)
clock = clock_get(CLOCK_APB2);
- } else {
- return -1;
- }
+ else
+ return -EINVAL;
- int_div = (25 * clock) / (4 * gd->baudrate);
+ int_div = (25 * clock) / (4 * baudrate);
tmp = ((int_div / 100) << USART_BRR_M_SHIFT) & USART_BRR_M_MASK;
frac_div = int_div - (100 * (tmp >> USART_BRR_M_SHIFT));
tmp |= (((frac_div * 16) + 50) / 100) & USART_BRR_F_MASK;
-
writel(tmp, &usart->brr);
- setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
return 0;
}
-static int stm32_serial_getc(void)
+static int stm32_serial_getc(struct udevice *dev)
{
- struct stm32_serial *usart =
- (struct stm32_serial *)usart_base[USART_PORT];
- while ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)
- ;
+ struct stm32_serial_platdata *plat = dev->platdata;
+ struct stm32_usart *const usart = plat->base;
+
+ if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)
+ return -EAGAIN;
+
return readl(&usart->dr);
}
-static void stm32_serial_putc(const char c)
+static int stm32_serial_putc(struct udevice *dev, const char c)
{
- struct stm32_serial *usart =
- (struct stm32_serial *)usart_base[USART_PORT];
+ struct stm32_serial_platdata *plat = dev->platdata;
+ struct stm32_usart *const usart = plat->base;
- if (c == '\n')
- stm32_serial_putc('\r');
+ if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)
+ return -EAGAIN;
- while ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)
- ;
writel(c, &usart->dr);
+
+ return 0;
}
-static int stm32_serial_tstc(void)
+static int stm32_serial_pending(struct udevice *dev, bool input)
{
- struct stm32_serial *usart =
- (struct stm32_serial *)usart_base[USART_PORT];
- u8 ret;
+ struct stm32_serial_platdata *plat = dev->platdata;
+ struct stm32_usart *const usart = plat->base;
- ret = readl(&usart->sr) & USART_SR_FLAG_RXNE;
- return ret;
+ if (input)
+ return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;
+ else
+ return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;
}
-static struct serial_device stm32_serial_drv = {
- .name = "stm32_serial",
- .start = stm32_serial_init,
- .stop = NULL,
- .setbrg = stm32_serial_setbrg,
- .putc = stm32_serial_putc,
- .puts = default_serial_puts,
- .getc = stm32_serial_getc,
- .tstc = stm32_serial_tstc,
-};
-
-void stm32_serial_initialize(void)
+static int stm32_serial_probe(struct udevice *dev)
{
- serial_register(&stm32_serial_drv);
-}
+ struct stm32_serial_platdata *plat = dev->platdata;
+ struct stm32_usart *const usart = plat->base;
+ int usart_port = -1;
+ int i;
+
+ for (i = 0; i < MAX_SERIAL_PORTS; i++) {
+ if ((u32)usart == usart_port_rcc_pairs[i][0]) {
+ usart_port = i;
+ break;
+ }
+ }
-__weak struct serial_device *default_serial_console(void)
-{
- return &stm32_serial_drv;
+ if (usart_port == -1)
+ return -EINVAL;
+
+ if (((u32)usart & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE)
+ setbits_le32(&STM32_RCC->apb1enr,
+ usart_port_rcc_pairs[usart_port][1]);
+ else if (((u32)usart & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE)
+ setbits_le32(&STM32_RCC->apb2enr,
+ usart_port_rcc_pairs[usart_port][1]);
+ else
+ return -EINVAL;
+
+ setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
+
+ return 0;
}
+
+static const struct dm_serial_ops stm32_serial_ops = {
+ .putc = stm32_serial_putc,
+ .pending = stm32_serial_pending,
+ .getc = stm32_serial_getc,
+ .setbrg = stm32_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_stm32) = {
+ .name = "serial_stm32",
+ .id = UCLASS_SERIAL,
+ .ops = &stm32_serial_ops,
+ .probe = stm32_serial_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
/*
* (C) Copyright 2015
- * Kamil Lulko, <rev13@wp.pl>
+ * Kamil Lulko, <kamil.lulko@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define CONFIG_STM32_GPIO
#define CONFIG_STM32_SERIAL
-/*
- * Configuration of the USART
- * 1: TX:PA9 RX:PA10
- * 2: TX:PD5 RX:PD6
- * 3: TX:PC10 RX:PC11
- * 6: TX:PG14 RX:PG9
- */
-#define CONFIG_STM32_USART 1
#define CONFIG_STM32_HSE_HZ 8000000
--- /dev/null
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <kamil.lulko@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SERIAL_STM32_H
+#define __SERIAL_STM32_H
+
+/* Information about a serial port */
+struct stm32_serial_platdata {
+ struct stm32_usart *base; /* address of registers in physical memory */
+};
+
+#endif /* __SERIAL_STM32_H */
#define _GNU_SOURCE
+#include <compiler.h>
#include <errno.h>
#include <env_flags.h>
#include <fcntl.h>
projects / platform / kernel / u-boot.git / commitdiff